80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 162

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
A14
B13
A12
A3
A4
C22
D2
D4
D11
D13
E6
E8
E10
E12
E14
E20
F7
F9
F11
F13
F17
G6
G8
TM0
TM1
TM2
TMS
TRST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
TMODE0
TMODE1
TMODE2
JTAG
JTAG
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
(VDD3, GND) / CMOS Input
162 of 172
TM[2:0]; MBIST Enable for use in testing on-chip memories.
MBIST is enabled when mben = 1. Internal pull-down ensures
disable if this pin is not driven.
TM[2:0]; MBIST Enable for use in testing on-chip memories.
TM[2:0]; MBIST Enable for use in testing on-chip memories.
JTAG Tap Port Mode Select
JTAG Tap Port Asynchronous Reset
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Advanced Datasheet*
March 19, 2007