SDA5523 Micronas Semiconductor, SDA5523 Datasheet
SDA5523
Related parts for SDA5523
SDA5523 Summary of contents
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MICRONAS Edition Sept. 10, 2004 6251-556-3DS DATA SHEET SDA 55xx TVText Pro MICRONAS ...
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SDA 55xx Contents Page Section Title 8 1. Introduction 8 1.1. General Features 8 1.1.1. External Crystal and Programmable Clock Speed 8 1.1.2. Microcontroller Features 9 1.1.3. Memory 9 1.1.4. Display Features 9 1.1.5. Acquisition Features 9 1.1.6. Ports 11 ...
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DATA SHEET Contents, continued Page Section Title 21 2.2.8.1.6. Program Status Word Register (PSW) 21 2.2.8.1.7. Stack Pointer (SP) 22 2.2.8.1.8. Data Pointer Register (DPTR). 22 2.2.8.2. CPU Timing 22 2.2.8.3. Addressing Modes 23 2.2.8.3.1. Register Addressing 23 2.2.8.3.2. Direct ...
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SDA 55xx Contents, continued Page Section Title 46 2.4.5. Functional Blocks 46 2.4.6. RAMs 46 2.4.7. Analog Blocks 46 2.4.8. Microcontroller 46 2.4.9. Ports 46 2.4.10. Initialization Phase 46 2.4.10.1. Acquisition 46 2.4.10.2. Display 47 2.5. Memory Organization 47 2.5.1. ...
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DATA SHEET Contents, continued Page Section Title 53 2.7.1.2. Mode 1 53 2.7.1.3. Mode 2 53 2.7.1.4. Mode 3 53 2.7.2. Timer/Counter 1: Mode Selection 53 2.7.2.1. Mode 2 53 2.7.2.2. Mode 3 54 2.7.3. Configuring the Timer/Counter Input 54 ...
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SDA 55xx Contents, continued Page Section Title 65 2.11.2. Registers 66 2.12. Sync System 66 2.12.1. General Description 66 2.12.1.1. Screen Resolution 66 2.12.1.1.1. Blacklevel Clamping Area 66 2.12.1.1.2. Border Area 67 2.12.1.1.3. Character Display Area 67 2.12.1.2. Sync Interrupts ...
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DATA SHEET Contents, continued Page Section Title 104 2.13.10. TVText Pro Characters 109 2.14. D/A Converter 109 2.14.1. Related Registers 110 3. Special Function Register (SFR) 110 3.1. SFR Register Block Index 110 3.2. SFR Register Index 114 3.3. SFR ...
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SDA 55xx TVText Pro Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The Micronas SDA 55xx TV microcontroller is dedi- cated to 8 bit applications for TV control and provides dedicated graphic features designed for ...
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DATA SHEET – ADC (4 channels, 8 bit) – UART 1.1.3. Memory – Non-multiplexed 8-bit data and 16…20-bit address bus (ROMless version) – Memory banking MByte (ROMless version) – 128 kByte on-chip program ROM – ...
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SDA 55xx IRAM 256X8 ADC WDT interface Capture control Peripheral PWM Bus Interface Port Logic UART SFRs Clock & Sync System Fig. 1–2: Block Diagram 10 Analog Mux ADC Memory Extension Stack 128X8 Program ROM 128KX8 Memory Extension Unit M8051S ...
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DATA SHEET 1.2. Overview of Current Versions and Packages for SDA 55xx Table 1–1: TVText Pro versions and packages overview Version Type – ROMless version SDA 5550M – 16 kByte RAM – ROMless version SDA 5550 – 16 kByte RAM ...
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SDA 55xx 2. Functional Description 2.1. Clock System 2.1.1. General Function The on-chip clock generator provides the TVTpro with its basic clock signal. The oscillator runs with an exter- nal crystal and the appropriate internal oscillator cir- cuitry (see Fig. ...
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DATA SHEET 2.1.3. Pixel Clock The second clock system is the pixel clock (f is programmable in a range from 10 … 32 MHz. It serves the output part of the display FIFO and the D/A converters. The pixel clock ...
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SDA 55xx 2.2. Slicer and Data Acquisition 2.2.1. General Function TVTPro provides a full digital data slicer including digi- tal H- and V-sync separation and digital sync process- ing. The acquisition interface is capable to process all known data services ...
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DATA SHEET 2.2.2.1. Distortion Processing After A/D conversion the digital CVBS bit stream is applied to internal circuitry which corrects the input signal for distortions created in the transmission chan- nel. In order to apply the right algorithm for the ...
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SDA 55xx 2.2.4. Acquisition Interface The acquisition interface manages the data transfer from between slicer and memory. From slicer to mem- ory first of all a bit synchronization is performed (Fram- ing Code (FC) check). Following this, the data is ...
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DATA SHEET That means if at least 855 Bytes (14767 Bytes in full channel mode) are reserved for the VBI buffer size in the RAM no VBI overflow will occur. The controller can start or stop the VBI data acquisition ...
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SDA 55xx 2.2.5. Related Registers The acquisition interface has only three SFR Regis- ters. The line and field parameters are stored in the RAM (RAM registers). They have to be initialized by software before starting the data acquisition. Table 2–2: ...
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DATA SHEET 2.2.5.1.2. Line Parameters Table 2–4: Line parameters Register Name 7 6 ACQLP0 DINCR[15:8] ACQLP1 DINCR[7:0] ACQLP2 NORM[2:0] ACQLP3 MLENGTH[2:0] ACQLP4 PERR[5:0] See Section 3. on page 110 for detailed register description. 2.2.6. Recommended Parameter Settings Table 2–5: Recommended ...
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SDA 55xx 2.2.7. Microcontroller 2.2.8. Architecture Every CPU machine cycle consists of 12 internal CPU clock periods. The CPU manipulates operands in two memory spaces: The program memory space, and the data memory space. The program memory address space is ...
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DATA SHEET exclusive-or, complement and rotate (right, left, or nib- ble swap). The register ACC is the accumulator, the register B is dedicated during multiply and divide and serves as both source and destination. During all other opera- tions the ...
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SDA 55xx 2.2.8.1.8. Data Pointer Register (DPTR). Table 2–8: Related registers Register Name 7 6 DPL DPH DPSEL See Section 3. on page 110 for detailed register description. The 16-bit Data Pointer Register DPTR is the concate- nation of registers ...
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DATA SHEET 2.2.8.3.1. Register Addressing Register addressing accesses the eight working regis- ters (R0 … R7) of the selected register bank. The PSW register flags RS1 and RS0 determine which reg- ister bank is enabled. The least significant three bits ...
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SDA 55xx from sourcing current into the external device that is driving the input pin not allowed to drive Port 3.6 to logic low level while reset state changes from the active to inactive state otherwise a special ...
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DATA SHEET Table 2–9: Ports and I/O-pins, continued Port I/O Default Function Toggle Control bit 1) P4(1) I/O A18 CSCR1(A18_P4_1) P4(2) I/O Port pin CSCR1(ENARW) P4(3) I/O Port pin CSCR1(ENARW) 1) P4(4) I/O A19 CSCR1(A19_P4_4) P4(7) I/O Port/VS in CSCR0(VS_OE, ...
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SDA 55xx 2.2.10. Instruction Set The assembly language uses the same instruction set and the same instruction opcodes as the 8051 micro- computer family. 2.2.10.1. Notes on Data Addressing Modes Rn – Working register R0 - R7. direct – 128 ...
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DATA SHEET 2.2.10.3. Instruction Set Description Table 2–11: Arithmetic operations Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, ...
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SDA 55xx Table 2–12: Logical operations Mnemonic ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ...
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DATA SHEET Table 2–13: Boolean variable manipulation Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Micronas Description ...
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SDA 55xx Table 2–14: Data transfer operations Mnemonic MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, ...
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DATA SHEET Table 2–15: Program and machine control operations Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit, ...
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SDA 55xx 2.2.10.4. Instruction Opcodes in Hexadecimal Order Table 2–16: Instruction opcodes in hexadecimal order Hex Number Mnemonic Code of Bytes 00 1 NOP 01 2 AJMP 02 3 LJMP INC 05 2 INC 06 ...
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DATA SHEET Table 2–16: Instruction opcodes in hexadecimal order Hex Number Mnemonic Code of Bytes 3A 1 ADDC 3B 1 ADDC 3C 1 ADDC 3D 1 ADDC 3E 1 ADDC 3F 1 ADDC AJMP 42 ...
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SDA 55xx Table 2–16: Instruction opcodes in hexadecimal order Hex Number Mnemonic Code of Bytes 76 2 MOV 77 2 MOV 78 2 MOV 79 2 MOV 7A 2 MOV 7B 2 MOV 7C 2 MOV 7D 2 MOV 7E ...
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DATA SHEET Table 2–16: Instruction opcodes in hexadecimal order Hex Number Mnemonic Code of Bytes B0 2 ANL B1 2 ACALL B2 2 CPL B3 1 CPL B4 3 CJNE B5 3 CJNE B6 3 CJNE B7 3 CJNE B8 ...
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SDA 55xx Table 2–16: Instruction opcodes in hexadecimal order Hex Number Mnemonic Code of Bytes E4 1 CLR E5 2 MOV E6 1 MOV E7 1 MOV E8 1 MOV E9 1 MOV EA 1 MOV EB 1 MOV EC ...
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DATA SHEET 2.3. Interrupt 2.3.1. Interrupt System External events and the real-time operation of on-chip peripherals require CPU service asynchronous to the execution of any particular section of code. To couple the asynchronous activities of these functions to nor- mal ...
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SDA 55xx 2.3.4. Enabling Interrupts Interrupts are enabled through a set of Interrupt Enable registers (IEN0, IEN1, IEN2, IEN3). Bits the Interrupt Enable registers each indi- vidually enable/disable a particular interrupt source. Overall control is provided ...
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DATA SHEET 2.3.6. Interrupt Priority For the purposes of assigning priority, the 24 possible interrupt sources are divided into groups determined by their bit position in the Interrupt Enable Registers. Their respective requests are scanned in the order as shown ...
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SDA 55xx 2.3.7. Interrupt Vectors When an interrupt is served, a long call instruction is executed to one of the locations listed in Table 2–21. Table 2–21: Interrupt vectors Interrupt Sources Register External Interrupt 0 IEN0 Timer 0 Overflow IEN0 ...
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DATA SHEET 2.3.8. Interrupt and Memory Extension When an interrupt occurs, the Memory Management Unit (MMU) carries out the following sequence of actions: 1. The MEX1 register bits are made available on SDATAO[7:0]. 2. The MEXSP register bits are made ...
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SDA 55xx 2.3.13. Interrupt Nesting The process whereby a higher-level interrupt request interrupts a lower-level interrupt service routine is called “nesting”. In this case the address of the next instruction in the lower-priority service routine is pushed onto the stack, ...
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DATA SHEET 2.3.15. Extension of Standard 8051 Interrupt Logic For more flexibility, SDA 55xx family provides a new feature for the status detection of external extra inter- rupts EX0 and EX1 in an edge-triggered mode. Now there is the possibility ...
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SDA 55xx 2.3.16. Interrupt Task Function The microcontroller records the active priority level(s) by setting internal flip-flop(s). Each interrupt level has its own flip-flop. The flip-flop corresponding to the inter- rupt level being serviced is reset when the microcon- troller ...
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DATA SHEET 2.3.19. Idle Mode Entering the idle mode is done by two consecutive instructions immediately following each other. The first instruction has to set bit IDLE (PCON.0) and must not set bit IDLS (PCON.5). The following instruction has to ...
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SDA 55xx 2.4. Reset 2.4.1. Reset Sources TVText Pro can be reset by two sources: 1. Externally by pulling down the reset pin RST. 2. Internally by Watch dog timer reset. Please note that both reset signals use the same ...
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DATA SHEET 2.5. Memory Organization The microcontroller has separate Program and Data memory spaces. Memory spaces can be further clas- sified as: – Program Memory – Internal Data Memory of 256 Bytes (CPU RAM) – Internal Extended Data Memory (XRAM) ...
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SDA 55xx 2.5.2. Internal Data RAM Internal Data RAM is split into CPU RAM and XRAM 2.5.2.1. CPU RAM 2.5.2.1.1. Address Space The internal CPU RAM (IRAM) occupies address space This space is further split into ...
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DATA SHEET 2.5.3. Memory Extension The controller provides four additional address lines A16, A17, A18 and A19. These additional address lines are used to access program and data memory space 1MByte. The extended memory space is split ...
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SDA 55xx 2.5.4. Instructions on which Memory Extension would act The following instruction are used to access the extended memory space: – LJMP – MOVC – MOVX – LCALL – ACALL – RET – RETI 2.5.4.1. Program Memory Banking (LJMP) ...
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DATA SHEET Fig. 2–5: PC and DPTR on different banks 2.5.4.7.1. Sample Code Fig. 2–6 shows an assembler program run, performing the following actions: 1. Start at bank 0 at 00000. 2. Set ISR-page to bank 2. 3. Jump to ...
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SDA 55xx 2.6.1.4. Mode 3 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first programmable 9 data bit and a stop bit (1). In fact, mode 3 is ...
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DATA SHEET 2.7. General Purpose Timers/Counters Two independent general purpose 16-bit timer/ counters are integrated for use to measure time inter- vals, pulse widths, counting events, and causing peri- odic (repetitive) interrupts. Both can be configured to operate as timer ...
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SDA 55xx 2.7.3. Configuring the Timer/Counter Input The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode) and TCON (timer con- trol). The input to the counter circuitry is from an exter- nal reference (for use ...
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DATA SHEET 2.8. Capture Reload Timer The capture control timer bit up counter, with special features suited for easier infrared decoding by measuring the time interval between two successive trigger events. Trigger events can be positive, negative ...
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SDA 55xx 2.8.3.6. Normal Capture Mode Normal capture mode is started by setting the RUN bit (0 --> 1) and PLG = 0, start = 0. Setting RUN bit will reload the counter with reload value and reset the overflow ...
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DATA SHEET 2.8.3.12. Counter Stop The counter can be stopped any time by resetting the RUN bit. If the counter is stopped and started again (reset and set the RUN bit), the counter reloads with the RELOAD value and reset ...
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SDA 55xx Table 2–34: Time resolution SD f PR1 PR sys 33.33 MHz 8.33 MHz RUN fcct P 3.3 RISE P 3.2 ...
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DATA SHEET 2.9. Pulse Width Modulation Unit The Pulse Width Modulation unit consists of 6 chan- nels with 8 bit resolution and 2 channels with 14 bit resolution PWM channels. PWM channels are pro- grammed via special function registers and ...
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SDA 55xx 2.9.4.2. 14-bit PWM The base frequency bit resolution channel is derived from the overflow of a eight bit counter. On every counter overflow, the enabled PWM lines would be set except in ...
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DATA SHEET 2.9.6. Power-Down, Idle and Power-save Mode In idle mode the pulse width modulation unit PWMU continues to function normally, unless it has been explicitly shut down by PSAVE(PERI). Note that in PSAVE mode all channels are frozen and ...
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SDA 55xx 2.9.8. Control Registers All control registers for the PWM are mapped in the SFR address space. Their address and bit description are given below. Note that the controller can write any time into these registers. However registers PWM_CPMP14_X ...
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DATA SHEET 2.10. Watchdog Timer The Watchdog timer bit up counter which can be programed to clock wdt count value of the watchdog timer is contained in the watchdog timer register WDT_high ...
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SDA 55xx Table 2–39: Maximum and minimum WDT overflow time period f system Min. 33.33 MHz Max. 33.33 MHz :2 f WDT :128 WDT_Rel WDT_Ctrl WDT_Refresh Fig. 2–9: Block Diagram 2.10.7. WDT as General Purpose Timer The watch dog timer ...
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DATA SHEET 2.11. Analog Digital Converter (CADC) TVTpro includes a four channel 8-bit ADC for control purposes. By means of these four input signals the controller is able to supervise the status four analog signals and take ...
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SDA 55xx 2.12. Sync System 2.12.1. General Description The display sync system is completely independent from the acquisition sync system (CVBS timing) and can either work as a sync master sync slave system. Talking about ‘H/V-Syncs’ in ...
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DATA SHEET 2.12.1.1.3. Character Display Area Characters and their attributes which are displayed inside this area are free programmable according to the specifications of the display generator (see also Section 2.13.2. on page 69). The start position of that area ...
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SDA 55xx 2.12.1.3. Related Registers Table 2–43: Related registers Register Name 7 6 SCR1 Reserved SCR0 RGB_D_[1:0] CISR0 L24 ADC bit addressable VLR1 ODD_Ev VLR0 HPR1 HPR0 SDV1 SDV0 SDH1 SDH0 HCR1 HCR0 BVCR BVCR0 EVCR1 EVCR0 SNDCSTL HYS CSCR0 ...
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DATA SHEET 2.13. Display The display is based on the requirements for a Level 1.5 Teletext and powerful additional enhanced OSD features. The display circuit reads the contents and attribute set- tings of the display memory and generates the RGB ...
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SDA 55xx 2.13.3. Display Memory The display memory is located inside the internal XRAM. The start address of the display memory is at memory address DISPOINT . This memory address is defined H by the user due to a pointer. ...
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DATA SHEET Table 2–45: Character display word: RAM location: Display memory, continued Byte Bit Name Function Pos. 16 CLUT1 Bit1/CLUT select 17 CLUT2 Bit2/CLUT select 18 FG0 Foreground color vector 19 FG1 20 FG2 2 21 BG0 Background color vector ...
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SDA 55xx 2.13.4.3. Address Range from 768 The address range from 768 to 1023 d address the DRCS characters. This range is split into three parts for 1-bit DRCS, 2-bit DRCS and 4-bit DRCS. The boundary between 1-bit DRCS and ...
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DATA SHEET Below some examples can be found to show how the character addressing depends on the boundary defini- tions: 2.13.4.3.1. Example 1 Boundary Pointer 1 set to 848 d Boundary Pointer 2 set to 928 d Character Address Description ...
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SDA 55xx 2.13.4.5. Character Individual Double Height Bit UH (Upper half, double height) marks the upper part of a double height character only active, if the DH bit (Double Height) is set to ‘1’. Table 2–49 shows the ...
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DATA SHEET 2.13.5. Global OSD Attributes Next to the parallel attributes stored inside character display word there are global attributes. The settings of the global attributes affect the full screen. The settings of the global OSD attributes are stored in ...
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SDA 55xx Table 2–51: Global OSD attributes, continued Byte Bit Name Pos. 0 CURVER3 1 POSHOR0 2 POSHOR1 3 POSHOR2 2 4 POSHOR3 5 POSHOR4 6 POSHOR5 7 POSVER0 0 POSVER1 1 POSVER2 2 POSVER3 3 POSVER4 3 4 GLBT0_BOX1 ...
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DATA SHEET Table 2–51: Global OSD attributes, continued Byte Bit Name Pos. 0 GDDH0 1 GDDH1 2 GDDH2 3 GLBT0_BOX0 5 4 GLBT1_BOX0 5 GLBT2_BOX0 6 BLA_BOX0 7 COR_BOX0 0 CHADRC0 1 CHADRC1 2 CHADRC2 3 CHAROM0 6 4 CHAROM1 ...
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SDA 55xx Table 2–51: Global OSD attributes, continued Byte Bit Name Pos. 0 SHEN 1 SHEAWE 2 SHCOL0 3 SHCOL1 8 4 SHCOL2 5 SHCOL3 6 SHCOL4 7 SHCOL5 0 CURCLUT0 1 CURCLUT1 2 CURCLUT2 3 FLRATE0 4 FLRATE1 9 ...
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DATA SHEET 2.13.6. Character Display Area Resolution Table 2–52: Character display area resolution DISALH4 DISALH3 … … See also Section 2.13.5. / Global Display Word (GDW) ...
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SDA 55xx Table 2–54: Horizontal cursor pixel offset within character matrix CURHOR3 CURHOR2 … See also Section 2.13.5. on page 75-Global Display Word (GDW) Table 2–55: Vertical cursor ...
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DATA SHEET The cursor is handled as a layer above the character display area. Pixels of the 2-bit cursor bit plane which are set to ‘00’ are transparent to the OSD/Video layer below. So the cursor can be transparent to ...
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SDA 55xx Example: DRCS-character stored at 896 : d row 10 pixel-shift: 7 horizontal vertical character-row/column: 5 horizontal vertical: d Fig. 2–12: Positioning of HW Cursor One out of 8 subCLUTs is used to ...
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DATA SHEET 2.13.7.1. Border Color Table 2–59: Border color settings BRDCOL5 BRDCOL4 BRDCOL3 … See also Section 2.13.5. on page 75-Global Display ...
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SDA 55xx Table 2–60: Full screen double height GDDH2 GDDH1 GDDH0 See also Section 2.13.5. on page 75-Global Display Word (GDW) 84 Display Area Full ...
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DATA SHEET 2.13.7.3. Flash Rate Control This attribute is used to control the flash rate for the full screen. All the characters on the screen for which flash is enabled are flashing with same frequency and in same phase. Table ...
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SDA 55xx 2.13.7.4. Transparency of Boxes For characters which are using subCLUT0 the trans- parency which is defined for the whole CLUT (see also Section 2.13.7.5. on page 88) can be overruled for foreground or background pixels. There are two ...
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DATA SHEET To decide the levels of COR and BLANK for BOX0 two global parameters are used. Table 2–63: COR/BLANK polarity of BOX0 COR_BOX0 BLA_BOX0 Description 0 0 Box transparency levels of COR and BLANK are overruled by: COR = ...
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SDA 55xx To decide the levels of COR and BLANK for BOX1 two global parameters are used. Table 2–65: COR/BLANK polarity of BOX1 COR_BOX1 BLA_BOX1 Description 0 0 Box transparency levels of COR and BLANK for BOX1 are overruled by: ...
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DATA SHEET The CLUT has a maximum width of 64 entries. The RGB values of the CLUT entries from 0-15 are hard- wired and can not be changed by software. The trans- parency for the hardwired CLUT values are set ...
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SDA 55xx Table 2–68: Organization of CLUT RAM Address CLUT CLUT No for ROM, Entry and 1-bit DRCS Character No. 0 Not available 1 Not available 2 Not available 3 0 Not available 4 Not available 5 Not available 6 ...
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DATA SHEET Table 2–68: Organization of CLUT, continued RAM Address CLUT CLUT No for ROM, Entry and 1-bit DRCS Character No. CLUTPOINT + CLUTPOINT + CLUTPOINT + CLUTPOINT ...
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SDA 55xx Table 2–68: Organization of CLUT, continued RAM Address CLUT CLUT No for ROM, Entry and 1-bit DRCS Character No. CLUTPOINT + CLUTPOINT + CLUTPOINT + CLUTPOINT ...
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DATA SHEET Table 2–68: Organization of CLUT, continued RAM Address CLUT CLUT No for ROM, Entry and 1-bit DRCS Character No. CLUTPOINT + CLUTPOINT + CLUTPOINT + CLUTPOINT ...
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SDA 55xx 2.13.7.5.3. CLUT Access for 4-bit DRCS Characters 4-bit DRCS characters are stored in the RAM. Within a 4-bit DRCS character a 4-bit color vector information is available for each pixel. By this 1 out of 16 color vec- ...
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DATA SHEET 2.13.7.7. Shadowing If shadowing is enabled the ROM characters and 1-bit DRCS characters of the characters are displayed by west shadow or east shadow. The color vector of the shadow is defined by software. The shadow color vec- ...
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SDA 55xx 2.13.7.8. Progressive Scan This feature is useful for TV-devices in which a frame consists of 1 field with 625 lines instead of 2 fields with 312.5 lines each. For this TV-fields on RGB-output lines are be repeated twice ...
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DATA SHEET Each character starts at a new Byte address. This causes, that for odd heights nibbles may be left free. Table 2–75: 1-Bit DRCS characters Char Address Bit7 CHAR 1 LINE 0 DRC1POINT PIXEL 0 H ...
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SDA 55xx Table 2–76: 2-Bit DRCS characters Char Address Bit7 CHAR 1 LINE 0 DRC2POINT PIXEL 0 H BIT 0 CHAR 1 LINE 0 DRC2POINT PIXEL 4 H BIT 0 CHAR 1 LINE 0 ...
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DATA SHEET Table 2–77: 4-Bit DRCS characters Char Address Bit7 CHAR 1 LINE 0 DRC4POINT PIXEL 0 H BIT 0 CHAR 1 LINE 0 DRC4POINT PIXEL 2 H BIT 0 CHAR 1 LINE 0 ...
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SDA 55xx 2.13.9. Memory Organization The memory organization concept of the OSD is based on a flexible pointer concept. All display mem- ory registers reside in the internal XRAM only. internal XRAM: Special Function Registers: POINTARRAY0 POINTARRAY1 Fig. 2–16: Memory ...
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DATA SHEET These 2 SFR pointers are used to point to 2 × 3 other pointers. These 6 pointers are pointing to the start address of the following memory areas: – Start address of character display area memory – Start ...
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SDA 55xx 2.13.9.1. Character Display Area The character display area consists of 3 Bytes for each character position of the character display area. These three Bytes are used to store the character display word described in Section ...
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DATA SHEET 2.13.9.5. Overview on the SFR Registers Other than the settings in the XRAM, SFR registers are used for OSD control. Table 2–80: SFR registers used for OSD control SFR Name Bit Address Programmable F8 EN_Ld_Cur Yes H F8 ...
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SDA 55xx 2.13.10. TVText Pro Characters Fig. 2–17: ROM Character Matrices 104 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET Fig. 2–18: ROM Character Matrices Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 105 ...
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SDA 55xx Fig. 2–19: ROM Character Matrices 106 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET Fig. 2–20: ROM Character Matrices Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 107 ...
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SDA 55xx Fig. 2–21: ROM Character Matrices 108 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET 2.14. D/A Converter TVTpro uses a 3 × 2-bit voltage D/A converter to gen- erate analog RGB output signals with a nominal ampli- tude of 0.7 V (also available: 0.5 V, 1.0 V and 1.2 V) peak-to-peak. 2.14.1. ...
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SDA 55xx 3. Special Function Register (SFR) 3.1. SFR Register Block Index Table 3–1: SFR block index Name ADC CRT DISPLAY DSYNC INTERRUPT MICRO PORT PWM SFRIF UART WATCHDOG 3.2. SFR Register Index Table 3–2: SFR register bits index Name ...
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DATA SHEET Table 3–2: SFR register bits index, continued Name ECC EDH EDV EHCR[7:0] En_DGOut En_Ld_Cur ENARW ENERCLK ENETCLK EPW ET0 ET1 EU EVCR[7:0] EVCR[9:8] EWT EX0 EX0F EX0R EX1 EX12 EX13 EX18 EX19 EX1F EX1R EX20 EX21 EX6 EXX0 ...
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SDA 55xx Table 3–2: SFR register bits index, continued Name IEX0 IEX1 INT IntSrc1 IntSrc1 IT0 IT1 L24 M0[1:0] M1[1:0] MAST MB[18:16] MB[19] MEXSP[6:0] MinH[7:0] MinL[7:0] MM MSIZ[7:0] MX[19] MX[19] MXM NB[19:16] O_E_P3_0 O_E_Pol Odd_Ev OSCPD ...
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DATA SHEET Table 3–2: SFR register bits index, continued Name REL RelH[7:0] RelL[7:0] REN Reserved Reserved RGB_D[1:0] RGB_G[1:0] RI RISE RS[1:0] RUN SD SDH[11:8] SDH[7:0] SDV[7:0] SDV[9:8] SEL SLI_ACQ SM0 SM1 SM2 SMOD SNC SND_H[2:0] SND_V[5:3] SP_[7:0] Start TAP TAP ...
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SDA 55xx 3.3. SFR Register Address Index Table 3–3: SFR subaddress index Sub SMOD PDS 88 TF1 TR1 89 GATE1 C_NT1 CB[19:16 ...
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DATA SHEET Table 3–3: SFR subaddress index, continued Sub L24 ADC ADW PWM_Tmr ...
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SDA 55xx Table 3–3: SFR subaddress index, continued Sub Odd_Ev FREQSEL(1 FREQSEL Addresses in bold are controller fix ...
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DATA SHEET 3.4. SFR Register Description Note: For compatibility reasons every undefined bit in a writeable register should be set to ’0’. Unde- fined bits in a readable register should be treated as “don’t care”! Table 3–4: SFR register description ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub IDLS h87[5] SD h87[4] GF1 h87[3] GF0 h87[2] PDE h87[1] IDLE h87[0] TCON h88 TF1 h88[7] TR1 h88[6] TF0 h88[5] TR0 h88[4] IE1 h88[3] IT1 h88[2] IE0 h88[1] IT0 h88[0] ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub C_NT0 h89[2] M0[1:0] h89[1:0] TL0 h8A TL0[7:0] h8A[7:0] TL1 h8B TL1[7:0] h8B[7:0] TH0 h8C TH0[7:0] h8C[7:0] TH1 h8D TH1[7:0] h8D[7:0] MEX1 h94 CB[19:16] h94[7:4] NB[19:16] h94[3:0] MEX2 h95 MM h95[7] ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub PSW hD0 CY hD0[7] AC hD0[6] F0 hD0[5] RS[1:0] hD0[4:3] OV hD0[2] F1 hD0[1] P hD0[0] ACC hE0 A[7:0] hE0[7:0] B hF0 B[7:0] hF0[7:0] MSIZ hFF MSIZ[7:0] hFF[7:0] SCON h98 ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub IEN0 hA8 EAL hA8[7] EAD hA8[5] EU hA8[4] ET1 hA8[3] EX1 hA8[2] ET0 hA8[1] EX0 hA8[0] IEN1 hA9 EDV hA9[5] EAV hA9[4] EXX1 hA9[3] EWT hA9[2] EXX0 hA9[1] EX6 hA9[0] ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub IP1 hAC G5P0 hAC[5] G4P0 hAC[4] G3P0 hAC[3] G2P0 hAC[2] G1P0 hAC[1] G0P0 hAC[0] IRCON hAD EXX1R hAD[7] EXX1F hAD[6] EXX0R hAD[5] EXX0F hAD[4] EX1R hAD[3] EX1F hAD[2] EX0R hAD[1] ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub IP0 hB8 G5P1 hB8[5] G4P1 hB8[4] G3P1 hB8[3] G2P1 hB8[2] G1P1 hB8[1] G0P1 hB8[0] CISR0 hC0 L24 hC0[7] ADC hC0[6] WTmr hC0[5] Micronas Dir Reset Range Function RW h00 Interrupt ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub AVS hC0[4] DVS hC0[3] PWtmr hC0[2] AHS hC0[1] DHS hC0[0] CISR1 hC8 CC hC8[7] ADW hC8[6] IEX1 hC8[1] IEX0 hC8[0] SNDCSTL hDF HYS hDF[6] 124 Dir Reset Range Function RW ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub SND_V[2:0] hDF[5:3] SND_H[2:0] hDF[2:0] WDT_rel hB1 WDTrel[7:0] hB1[7:0] WDT_ctrl hB2 WDT_in hB2[7] WDT_start hB2[6] WDT_narst hB2[5] WDT_rst hB2[4] WDT_refresh hB3 WDT_ref hB3[7] WDT_tmr hB3[6] WTmr_strt hB3[5] WTmr_ov hB3[4] WDT_low hB4 ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub WDT_high hB5 WDThi[7:0] hB5[7:0] CRT_rell hB7 RelL[7:0] hB7[7:0] CRT_relh hB9 RelH[7:0] hB9[7:0] CRT_capl hBA CapL[7:0] hBA[7:0] CRT_caph hBB CapH[7:0] hBB[7:0] CRT_mincapl hBC MinL[7:0] hBC[7:0] CRT_mincaph hBD MinH[7:0] hBD[7:0] CRT_con0 hBE ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub PWM_comp8_0 hC1 PC80[7:0] hC1[7:0] PWM_comp8_1 hC2 PC81[7:0] hC2[7:0] PWM_comp8_2 hC3 PC82[7:0] hC3[7:0] PWM_comp8_3 hC4 PC83[7:0] hC4[7:0] PWM_comp8_4 hC5 PC84[7:0] hC5[7:0] PWM_comp8_5 hC6 PC85[7:0] hC6[7:0] PWM_comp14_0 hC7 PC140[7:0] hC7[7:0] PWM_comp14_1 hC9 ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub PWM_EN hCE PE[7:0] hCE[7:0] CADC0 hD1 CADC0[7:0] hD1[7:0] CADC1 hD2 CADC1[7:0] hD2[7:0] CADC2 hD3 CADC2[7:0] hD3[7:0] CADC3 hD4 CADC3[7:0] hD4[7:0] CADCCO hD5 ADWULE hD5[4] AD[3:0] hD5[3:0] 128 Dir Reset Range ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub PSAVEX hD7 Clk_src hD7[2] PLL_Res hD7[1] PLLS hD7[0] PSAVE hD8 CADC hD8[4] WAKUP hD8[3] SLI_ACQ hD8[2] DISP hD8[1] PERI hD8[0] Micronas Dir Reset Range Function SFRIF RW h00 Power Save ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub STRVBI hD9 ACQON hD9[7] Reserved hD9[6] ACQ_STA hD9[5] VBIADR[3:0] hD9[3:0] PCLK1 hDA PF[10:8] hDA[3:0] PCLK0 hDB PF[7:0] hDB[7:0] SCR1 hE1 Reserved hE1[7] RGB_G[1:0] hE1[6:5] 130 Dir Reset Range Function RW ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub COR_BL hE1[4] VSU[3:0] hE1[3:0] SCR0 hE2 RGB_D[1:0] hE2[7:6] HP hE2[5] VP hE2[4] INT hE2[3] Micronas Dir Reset Range Function RW 3-Level Contrast Reduction Output By means of COR_BL the user ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub SNC hE2[2] VCS hE[1] MAST hE[0] SDV1 hE3 SDV[9:8] hE3[1:0] SDV0 hE4 SDV[7:0] hE4[7:0] SDH1 hE5 SDH[11:8] hE5[3:0] SDH0 hE6 SDH[7:0] hE6[7:0] HCR1 hE7 EHCR[7:0] hE7[7:0] 132 Dir Reset Range ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub HCR0 hE9 BHCR[7:0] hE9[7:0] BVCR hEA BVCR[9:8] hEA[1:0] BVCR0 hEB BVCR[7:0] hEB[7:0] EVCR1 hEC EVCR[9:8] hEC[1:0] EVCR0 hED EVCR[7:0] hED[7:0] VLR1 hEE Odd_Ev hEE[6] Micronas Dir Reset Range Function RW ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub VSU2[3:0] hEE[5:2] VL[9:8] hEE[1:0] VLR0 hEF VL[7:0] hEF[7:0] HPR1 hF1 HPR[11:8] hF1[3:0] HPR0 hF2 HPR[7:0] hF2[7:0] 134 Dir Reset Range Function RW 0 0..15 Vertical Set Up Time 2 (slave ...
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DATA SHEET Table 3–4: SFR register description, continued Name Sub POINTARRAY1_1 hF3 Point1[13:8] hF3[7:0] POINTARRAY1_0 hF4 Point1[7:0] hF4[7:0] POINTARRAY0_1 hF5 Point0[13:8] hF5[7:0] POINTARRAY0_0 hF6 Point0[7:0] hF6[7:0] OSD_ctrl hF8 En_Ld_Cur hF8[3] En_DGOut hF8[2] Dis_Cor hF8[1] Dis_Blank hF8[0] TAP hF9 TAP hFA ...
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SDA 55xx Table 3–4: SFR register description, continued Name Sub VS_OE hDD[2] O_E_P3_0 hDD[1] O_E_Pol hDD[0] CSCR1 hDE IntSrc1 hDE[7) IntSrc0 hDE[6] ENARW hDE[3] A19_P4_4 hDE[2] A18_P4_1 hDE[1] A17_P4_0 hDE[0] 136 Dir Reset Range Function RW h00 0: P4.7 alternate ...
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DATA SHEET 3.5. ACQ Register Block Index Table 3–5: ACQ block index Name FIELD_PARAMETER LINE_PARAMETER 3.6. ACQ Register Index Table 3–6: ACQ register bits index Name FC3[15:8] FC3[7:0] FC3MASK[15:8] FC3MASK [7:0] FC1[7:0] AGDON AFRON ANOON GDPON GDNON FREON NOION FULL ...
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SDA 55xx 3.7. ACQ Register Address Index Table 3–7: ACQ subaddress index Sub 7 6 h0000 FC3[15:8] h0001 FC3[7:0] h0002 FC3MASK[15:8] h0003 FC3MASK [7:0] h0004 FC1[7:0] h0005 AGDON AFRON h0006 NOISE(0) FREATTF h0007 LEOFLI[11:8] h0008 LEOFLI[7:0] h000D DINCR[15:8] h000E DINCR[7:0] ...
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DATA SHEET 3.8. ACQ Register Description Table 3–8: ACQ register description Name Addr ACQFP0 h0000 FC3[15:8] h0000[7:0] ACQFP1 h0001 FC3[7:0] h0001[7:0] ACQFP2 h0002 FC3MASK[15:8] h0002[7:0] ACQFP3 h0003 FC3MASK [7:0] h0003[7:0] ACQFP4 h0004 FC1[7:0] h0004[7:0] ACQFP5 h0005 AGDON h0005[7] AFRON h0005[6] ...
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SDA 55xx Table 3–8: ACQ register description, continued Name Addr FULL h0005[0] ACQFP6 h0006 NOISE(0) h0006[7] FREATTF h0006[6] STAB h0006[5] VDOK h0006[4] FIELD h0006[3] NOISE(1) h0006[2] GRDON h0006[1] 140 Dir Sync Reset Range Function 0..1 Full Channel ...
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DATA SHEET Table 3–8: ACQ register description, continued Name Addr GRDSIGN h0006[0] ACQFP7 h0007 LEOFLI[11:8] h0007[7:4] ACQFP8 h0008 LEOFLI[7:0] h0007[3:0] ACQLP0 h000D DINCR[15:8] h000D[7:0] ACQLP1 h000E DINCR[7:0] h000E[7:0] ACQLP2 h000F NORM[2:0] h000F[7:5] FCSEL[1:0] h000F[4:3] Micronas Dir Sync Reset Range Function ...
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SDA 55xx Table 3–8: ACQ register description, continued Name Addr FC1ER h000F[2] VCR h000F[1] ACQLP3 h0010 MLENGTH[7:5] h0010[7:5] ALENGTH[4:3] h0010[4:3] CLKDIV[2:0] h0010[2:0] 142 Dir Sync Reset Range Function this bit is ’1’ the FC1 check is ...
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DATA SHEET Table 3–8: ACQ register description, continued Name Addr ACQLP4 h0011 PERR[7:2] h0011[7:2] TLDE h0011[1] FCOK h0011[0] Micronas Dir Sync Reset Range Function RW HS h0000 Phase Error Watch Dog (detection of test line CCIR331a or ...
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SDA 55xx 4. Specifications 4.1. Outline Dimensions for PSDIP52-1 Package Fig. 4–1: PSDIP52-1: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO Weight approximately 5.13 g 144 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET 4.2. Outline Dimensions for PSDIP52-2 Package Fig. 4–2: PSDIP52-2: Plastic Shrink Dual In-line Package, 52 leads, 600 mil Ordering code: PO Weight approximately 5.92 g Micronas Sept. 10, 2004; 6251-556-3DS SDA 55xx 145 ...
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SDA 55xx 4.3. Outline Dimensions for PMQFP64-1 Package Fig. 4–3: PMQFP64-1: Plastic Metric Quad Flat Package, 64 leads, 14 × 14 × Ordering code: BS Weight approximately 0.95 g 146 3 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET 4.4. Outline Dimensions for PLCC84-1 Package Fig. 4–4: PLCC84-1: Plastic Leaded Chip Carrier, 84 leads, 29.4 × 29.4 × 3.8 mm Ordering code: WA Weight approximately 6.72 g Micronas 3 Sept. 10, 2004; 6251-556-3DS SDA 55xx 147 ...
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SDA 55xx 4.5. Outline Dimensions for PMQFP100-1 Package Fig. 4–5: PMQFP100-1: Plastic Metric Quad Flat Package, 100 leads, 14 × 20 × 2.7 mm Ordering code: QB Weight approximately 1.7 g 148 3 Sept. 10, 2004; 6251-556-3DS DATA SHEET Micronas ...
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DATA SHEET 4.6. Pin Connections and Short Descriptions NC = not connected, leave vacant not used, leave vacant Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52-2 − − − − ...
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SDA 55xx Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52-2 − − − 19 − − − ...
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DATA SHEET Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 ...
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SDA 55xx Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 ...
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DATA SHEET Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 ...
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SDA 55xx Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 100 8 154 ...
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DATA SHEET 4.7. Port Alternate Functions Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 ...
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SDA 55xx Pin No. PMQFP PMQFP PSDIP PLCC 100-1 64-1 52-1 84-1 52 ...
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DATA SHEET 4.8. Pin Descriptions Pin numbers refer to the PMQFP100-1 package. Pin D0, D1, D2, D3 − Data bus for external memory or data RAM. Pin 5, XROM − This pin must be pulled low ...
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SDA 55xx Pin 53, XTAL1 − Input of the inverting oscillator ampli- fier. Pin 54, NC − Pin is not connected. Pin 57, 58, 59 − Red, Green, Blue. Pin 60, BLANK/COR − Blanking and contrast reduc- ...
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DATA SHEET 4.9. Pin Configurations FL_PGM VDD 2.5 V VSS VDD 3.3 V A14 A12 A13 A7 FL_RST ...
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SDA 55xx P1.1 NC P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 NC P0.6 Fig. 4–7: PMQFP64-1 package 160 NC B BLANK/COR VDD 2.5 V VSS VDD 3 ...
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DATA SHEET VDD 2 VSS 10 43 VDD 3 CVBS ...
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SDA 55xx P4.2 P4.3 RST XTAL2 55 XTAL1 56 VSSA VDDA 2 ...
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DATA SHEET 4.10. Electrical Characteristics 4.10.1. Absolute Maximum Ratings Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is ...
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SDA 55xx 4.10.2. Recommended Operating Conditions Functional operation of the device beyond those indicated in the “Recomended Operating Conditions/Characteris- tics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are ...
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DATA SHEET 4.10.3. Characteristics Symbol Parameter Supply I Digital Supply Current for 3.3 V 3.3 V Domain I Digital Supply Current for 2.5 V 2.5 V Domain I Analog Power Supply Current ANA I Idle Mode Supply Current IDLE (with ...
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SDA 55xx Symbol Parameter CVBS-Input C Pin Capacitance P Z Input Impedance P C External Coupling CPL1 Capacitance R Source Impedance Z V Overall CVBS Amplitude CVBS V CVBS Sync Amplitude SYNC V TXT Data Amplitude DATA RGB-Outputs C Load ...
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DATA SHEET Symbol Parameter Data Bits T Output Rise Time r T Output Fall Time f C Load Capacitance L C Pin Capacitance I Control Bit CORBL=0, BLANK only T Output Rise Time r T Output Fall Time f V ...
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SDA 55xx Symbol Parameter VSYNC T Input Rise Time r T Input Fall Time f T Input Pulse Width IPWV T Output Rise time r T Output Fall Time f C Load Capacitance L C Pin Capacitance I V Input ...
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DATA SHEET 4.10.4. Timings 4.10.4.1. Sync Vsync Hsync Line i Fig. 4–10: H/V-Sync-Timing (Sync Master Mode) Equalizing pulses VCS Horizontal pulse VCS T T HPVCS DEP T T HPR HPR Fig. 4–11: VCS-Tming (Sync Master Mode) Micronas T OPWV T ...
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SDA 55xx 4.10.4.2. Program Memory Read Cycle State 5 A PSEN D t AVIV Parameter Frequency of internal clock Instruction read cycle time PSEN Pulse width PSEN to valid instruction in Instruction hold after PSEN Address to valid instruction in Fig. 4–12: Program Memory Read Cycle 170 t CYC PLPH t PHIX t PLIV valid ...
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DATA SHEET 4.10.4.3. Data Memory Read Cycle State Parameter Frequency of internal clock Data read cycle time RD Pulse width RD to valid data in Data hold after RD Address to valid data in Fig. 4–13: ...
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SDA 55xx 4.10.4.4. Data Memory Write Cycle State AVDV Parameter Frequency of internal clock Data write cycle time WR Pulse width WR to data out Data hold after WR Address to valid data out Fig. ...
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DATA SHEET 4.10.4.5. Blank/Cor Signal Range V DD 3.3 Contrast reduction don't care; blank on 2.4V undef ined 1 /3VD D3. 3+1 50m V Contrast reduction on; blank off 1/3VD D 3.3- 150 mV undefined 0.4V Contrast reduction off; blank ...
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SDA 55xx 5. Applications XTAL1 6 MHz XTAL2 HS/SC Sandcastle (max. 2.5 V) +3.3 V RST# +3.3 V VDD3.3 +2,5 V VDD2.5 (RGB) +2,5 V VDD2.5 (ADC) Fig. 5–1: Application Diagram 174 SDA 5550 only Up ...
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DATA SHEET Micronas Intentionally Vacant Sept. 10, 2004; 6251-556-3DS SDA 55xx 175 ...
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SDA 55xx 6. Data Sheet History 1. Data Sheet: “SDA 55xx TVText Pro”, July 27, 2001, 6251-556-1DS. First release of the data sheet. 2. Data Sheet: “SDA 55xx TVText Pro”, March 23, 2004, 6251-556-2DS. Second release of the data sheet. ...