SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 132

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
132
Name
SNC
VCS
MAST
SDV1
SDV[9:8]
SDV0
SDV[7:0]
SDH1
SDH[11:8]
SDH0
SDH[7:0]
HCR1
EHCR[7:0]
Sub
hE2[2]
hE[1]
hE[0]
hE3
hE3[1:0]
hE4
hE4[7:0]
hE5
hE5[3:0]
hE6
hE6[7:0]
hE7
hE7[7:0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
0
h20
32
h00
0
h48
72
h0A
10
Sept. 10, 2004; 6251-556-3DS
Range
0..1
0..1
0..3
0..255
0..15
0..255
0..255
Function
Sandcastle Sync (Slave mode only)
To input pins are reserved for synchronisation. These input pins can
be used as two separated sync inputs or as one single sync input. If
two separated sync inputs is selected horizontal syncs are fed in at H
pin and vertical syncs are fed in a V pin. If one single input pin is
selected the H pin is used as a sandcastle input pin.
0: H/V-sync input at H/V pins
1: Sancastle input H pin
Video Composite Sync
VCS defines the sync output at pin V (master mode only)
0: At pin V the vertical sync appears
1: At pin V a composite sync signal (including equalizing pulses, H-
Sync and V_Sync) is generated (VCS). The length of the equalizing
pulses have fixed values as described in the timing specifications.
Note: Don’t forget to set registers VLR and HPR (64 µs) according
to your requirements.
Master/Slave Mode
This bit defines the configuration of the sync system (master or slave
mode) and also the direction (input/output) of the V, H pins.
0: Slave mode. H, V pins are configured as inputs
1: Master mode. H, V pins are configured as outputs.
Note: Switching from slave to master mode resets the internal H,
V counters in that way, that the phase shift during the switch can
be minimized. In slave mode registers VLR and HPR are not used.
DSync V Delay 1
Vertical Sync Delay (master and slave mode)
This register defines the delay (in lines) from the vertical sync to the
first line of character display area on the screen.
DSync V Delay 0
Vertical Sync Delay (master and slave mode)
This register defines the delay (in lines) from the vertical sync to the
first line of character display area on the screen.
DSync H Delay 1
Horizontal Sync Delay (master and slave mode)
This register defines the delay (in pixels) from the horizontal sync to
the first pixel character display area on the screen.
DSync H Delay 0
Horizontal Sync Delay (master and slave mode)
This register defines the delay (in pixels) from the horizontal sync to
the first pixel character display area on the screen.
DSync H Clamp End
End of Horizontal Clamp Phase (master and slave mode)
This register defines the end of the horizontal clamp phase from the
positive edge of the horizontal sync impulse (at normal polarity). The
end of clamp phase can be calculated by the following formula:
tH_clmp_e = 480 ns * EHCR
If EHCR is smaller than BHCR the clamp phase will appear during
Hsync.
DATA SHEET
Micronas