SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 118

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
118
Name
IDLS
SD
GF1
GF0
PDE
IDLE
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TMOD
GATE1
C_NT1
M1[1:0]
GATE0
Sub
h87[5]
h87[4]
h87[3]
h87[2]
h87[1]
h87[0]
h88
h88[7]
h88[6]
h88[5]
h88[4]
h88[3]
h88[2]
h88[1]
h88[0]
h89
h89[7]
h89[6]
h89[5:4]
h89[3]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
h00
0
0
0
0
0
0
0
0
h00
0
0
0
0
Sept. 10, 2004; 6251-556-3DS
Range
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..3
0..1
Function
Idle Start Bit
0: Idle Mode not started.
1: Idle Mode started.
The instruction that sets this bit is the last instruction before entering
idle mode. Additionally, this bit is protected by a delay cycle. Idle mode
is entered, if and only if bit IDLE was set by the previous instruction.
Once set, this bit is cleared by hardware and always reads out a 0.
Slow-Down Bit
0: Slow-down mode is disabled.
1: Slow-down mode is enabled.
This bit is set to indicate the external clock generating circuitry to slow
down the frequency. This bit is not protected by a delay cycle.
Power Control
General purpose flag bits
For user.
Power-Down Mode Enable Bit
When set, a delay cycle is started. The following instruction can then
set the device into power down mode. Once set, this bit is cleared by
hardware and always reads out a 0.
Idle Start Bit
0: Idle Mode not started.
1: Idle Mode started.
The instruction that sets this bit is the last instruction before entering
idle mode. Additionally, this bit is protected by a delay cycle. Idle mode
is entered, if and only if bit IDLE was set by the previous instruction.
Once set, this bit is cleared by hardware and always reads out a 0.
The CADC is switched off but the CADC-Wake-Up-Unit is active.
Timer/Counter Control
Timer 1 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer 1 run control bit. Set/cleared by software to turn timer/counter
on/off.
Timer 0 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer 0 run control bit. Set/cleared by software to turn timer/counter
on/off.
Interrupt 1 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupts. IT1 = 1 selects transition-
activated external interrupts.
Interrupt 0 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt 0 type control bit.
Set/cleared by software to specify falling edge/low level triggered
external interrupts. IT0 = 1 selects transition-activated external inter-
rupts.
Timer/Counter Mode Control
Timer/Ctr Mode
Timer/Ctr Mode
Timer/Ctr Mode
Gating control when set. Timer/counter ëxí is enabled only while
ëINTxí pin is high and ëTRxí control pin is set. When cleared, timer ëxí
is enabled, whenever ëTRxí control bit is set.
DATA SHEET
Micronas