SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 67

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.12.1.1.3. Character Display Area
Characters and their attributes which are displayed
inside this area are free programmable according to
the specifications of the display generator (see also
Section 2.13.2. on page 69). The start position of that
area can be shifted in horizontal and vertical direction
by programming the horizontal and vertical sync delay
registers (SDH and SDV). The size of that area is
defined by the instruction FSR in the display generator.
Registers which allow to set up the screen and sync
parameters are given in Table 2–41.
The user has to take care of setting PFR and SDH so
that SDH/PFR is greater than 2 µs.
Table 2–42 lists some of the possible display modes.
Table 2–41: Overview on sync register settings
Table 2–42: Possible display modes
Micronas
Parameters
Sync Control Register
VL - Lines / Field
T
F
T
T
BVCR - Beginning
of Vertical Clamp Phase
EVCR - End
of Vertical Clamp Phase
T
of Horizontal Clamp Phase
T
of Horizontal Clamp Phase
50 Hz/100 Hz
50 Hz
50 Hz
100 Hz
100 Hz
h-period
pixel
vsync_delay
hsync_delay
h_clmp_b
h_clmp_e
- Pixel Frequency
- Horizontal Period
- Beginning
- End
- Sync Delay
- Sync Delay
Character Display Mode
40 × 25
64 × 25
40 × 25
64 × 25
Register
SCR
VLR
HPR
PClk
SDV
SDH
BVCR
EVCR
BHCR
EHCR
Sept. 10, 2004; 6251-556-3DS
Min. Value
No min/max general setup
1 line
15 µs
10 MHz
4 lines
32 pixel
1 line
1 line
0 µs
0 µs
Note that the Pixel clock (Pclk) must be appropriately
selected to the nearest value in the registers Pclk 0
and Pclk 1.
Table 2–42 serves as an example,. The freely pro-
grammable Pixel clock between 10 to 32 MHz makes it
possible to adjust and fine tune the display as per
application requirement.
2.12.1.2. Sync Interrupts
The sync unit delivers interrupts (Horizontal and verti-
cal interrupt) to the controller to support the recogni-
tion of the frequency of an external sync source. These
interrupts are related to the positive edge of the non
delayed horizontal and vertical impulses which can be
seen at pins HSYNC and VSYNC.
Pclk
12 MHz
16 MHz
24 MHz
32 MHz
Max. Value
1024 lines
122.8 µs
32 MHz
1024 lines
2048 pixel
1024 lines
1024 lines
122.8 µs
122.8 µs
T
40 µs
48 µs
20 µs
24 µs
Character display area
Step
1 line
30 ns
73.25 kHz
1 line
1 pixel
1 line
1 line
480 ns
480 ns
SDA 55xx
625 lines
32 lines
Default
64 µs
12.01 MHz
72 pixel
line 0
line 4
0 µs
4.8 µs
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