SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 45

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.3.19. Idle Mode
Entering the idle mode is done by two consecutive
instructions immediately following each other. The first
instruction has to set bit IDLE (PCON.0) and must not
set bit IDLS (PCON.5). The following instruction has to
set bit IDLS (PCON.5) and must not set bit IDLE
(PCON.0). Bits IDLE and IDLS will automatically be
cleared after having been set. This double-instruction
sequence is implemented to minimize the chance of
unintentionally entering the idle mode. The following
instruction sequence may serve as an example:
ORL
bit IDLS must not be set.
ORL
bit IDLE must not be set.
The instruction that sets bit IDLS is the last instruction
executed before going into idle mode.
Concurrent setting of the enable and the start bits
does not set the device into the respective power sav-
ing mode.
The idle mode can be terminated by activation of any
enabled interrupt (or a hardware reset). The CPU-
operation is resumed, the interrupt will be serviced and
the next instruction to be executed after RETI-instruc-
tion will be the one following the instruction that set the
bit IDLS. The port state and the contents of SFRs are
held during idle mode.
Entering Idle mode disables, VADC, Acquisition, Slicer,
Display, CADC and DAC. However note that CADC
Wake up unit is still operational. Leaving idle mode
brings them to their original power save configuration
(See Section 2.3.21.).
2.3.20. Power-down Mode
Entering the power-down mode is done by two consec-
utive instructions immediately following each other.
The first instruction has to set bit PDE (PCON.1) and
must not set bit PDS (PCON.6). The following instruc-
tion has to set bit PDS (PCON.6) and must not set bit
PDE (PCON.1). Bits PDE and PDS will automatically
be cleared after having been set.
This double-instruction sequence is implemented to
minimize the chance of unintentionally entering the
power-down mode. The following instruction sequence
may serve as an example:
ORL
PDS must not be set.
ORL
PDE must not be set.
Micronas
PCON,#00000001
PCON,#00100000
PCON,#00000010
PCON,#01000000
B
B
B
B
;Set bit IDLE,
;Set bit IDLS,
;Set bit PDE, bit
;Set bit PDS, bit
Sept. 10, 2004; 6251-556-3DS
The instruction that sets bit PDS is the last instruction
executed before going into power-down mode.
Concurrent setting of the enable and the start bits
does not set the device into the respective power sav-
ing mode.
If idle mode and power-down mode are invoked simul-
taneously, the power-down mode takes precedence.
The only exit from power-down mode is a hardware
reset. The reset will redefine all SFRs, but will not
change the contents of internal RAM.
2.3.21. Power-save Mode
Bits in the PSAVE register individually enable and dis-
able different major blocks in the IC. Note that
power-save mode is independent of Idle and
power-down mode. In case of idle mode, blocks which
are in power save mode remain in power-save mode.
Entering the power down mode with power-save mode
is possible. However leaving the power down mode
(reset) would initialize all the power save register bits.
Note that power-save mode has a higher priority then
idle mode.
2.3.22. Slow-Down Mode
SD bit in PCON register when sets divides the system
frequency by 4. During the normal operation TVT Pro
is running with 33.33 MHz and in SD mode TVT Pro
runs with 8.33 MHz. In slow-down mode the slicer,
Acquisition and display are disabled regardless of
power-save mode or other modes. All the pending
request to the bus by these blocks are masked off.
Leaving slow-down mode restores the original status
of these blocks.
SDA 55xx
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