SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 46

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.4. Reset
2.4.1. Reset Sources
TVText Pro can be reset by two sources:
1. Externally by pulling down the reset pin RST.
2. Internally by Watch dog timer reset.
Please note that both reset signals use the same sig-
nal path however a Watchdog reset does not reset the
clock PLL.
2.4.2. Reset Filtering
The RST pin uses a filter with a delay element, which
suppresses jitter and spikes in the range of 25 ns to
75 ns.
2.4.3. Reset Duration
With the active edge of the RST an internal signal
resets all the flip flops asynchronously. The internal
signal is released synchronously to the internal clock
when it is stable as described below.
The minimum duration of the external reset signal
depends on the time required for the SDA55xx internal
crystal oscillator to reach it’s full amplitude swing and
is dependent on the crystal used.
During the period when the RST pin is held low, the
PLL is initialized and it gets locked. The high going
reset pulse then initiates a sequence which requires
one machine cycle (12 clock cycles) to initialize the
microcontroller and all other registers and peripherals.
2.4.4. Registers
Upon reset, all the registers are initialized to the values
as defined in Section 3. on page 110.
2.4.5. Functional Blocks
After reset all the functional blocks will be in a defined
known state. Microcontroller, acquisition and display
will not have any pending bus requests after reset.
2.4.6. RAMs
The HW reset and its related logic does not initialize
any RAMs.
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Sept. 10, 2004; 6251-556-3DS
2.4.7. Analog Blocks
After the power up reset the DAC will output a fixed
value. ADC and the ADC wake up unit do not generate
any interrupts till the 12 cycle long reset sequence is
completed.
2.4.8. Microcontroller
After the reset sequence the program counter initial-
izes to 0000
the ROM. Location 0000H to 0002H are reserved for
the a jump instruction to the initialization routine.
2.4.9. Ports
With the reset all ports are set in to the input mode.
Exception are Port 4.0, 4.1 and 4.4, which by default
after reset are assigned as data outputs for the
address lines A17, A18, A19.
2.4.10. Initialization Phase
2.4.10.1. Acquisition
After the reset the Acquisition will not generate any
memory accesses to the RAM, due to the fact that the
Acq_start bit is initialized to ‘0’. The microcontroller
should then initialize the VBI buffer and set the
ACQ_start bit (by software). The Acquisition will not
generate any accesses to the RAM if the H / V syn-
chronization is not achieved.
2.4.10.2. Display
After reset the DACs will output a fix value as defined
by En_DGOut, which is reset to ‘0’. COR_BL is reset to
a level indicating COR = ‘0’ and BLank = ‘1’.
The microcontroller should initialize the display mem-
ory and set the En_DGOut (OCD_Ctrl) bit.
H
and starts execution from this location in
DATA SHEET
Micronas