SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 129

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
Table 3–4: SFR register description, continued
Micronas
Name
PSAVEX
Clk_src
PLL_Res
PLLS
PSAVE
CADC
WAKUP
SLI_ACQ
DISP
PERI
Sub
hD7
hD7[2]
hD7[1]
hD7[0]
hD8
hD8[4]
hD8[3]
hD8[2]
hD8[1]
hD8[0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
h00
h00
h00
hF4
1
1
1
0
0
Sept. 10, 2004; 6251-556-3DS
Range
0 ..1
0 ..1
0 ..1
0..1
0..1
0..1
0..1
0..1
SFRIF
Function
Power Save Extra Register
Clock Source
0:200 MHz PLL (33.33 MHz system clock) selected.
1: PLL is bypassed oscillator clock 6 MHz (3 MHz system clock
selected).
In this mode slicer, acquisition, DAC and display generator are
disabled.
PLL Reset
0:PLL not reset.
1:PLL reset.
PLL reset sequence requires that PLL_res = 1 for 10 µs then
PLL_res = 0, after that 150 µs are required till PLL is locked.
PLL Sleep
0:Power-save mode not started.
1:Power-save mode started.
Before the PLL is switched to power-save mode (PLLS = 1), the SW
has to switch the clock source from 200 MHz PLL clock to the 6 MHz
oscillator clock (CLK_src = 1).
To switch back to the normal mode, software has to end the PLL
power save mode (PLLS = 0), reset the PLL for 10 µs (3 machine
cycles), PLL_res = 1 the back to 0, wait for 150 µs (38 machine
cycles) and then switch back to the PLL clock.
Power Save Register
Power Save CADC
0: Power-save mode not started.
1: Power-save mode started.
In Power save mode CADC is disabled but the CADC-Wake-Up-Unit is
active.
Power Save CADC-Wake-Up-Unit
0: Power-save mode not started.
1: Power-save mode started.
In power-save mode the CADC-Wake-Up-Unit is disabled.
Power-save mode of wake up unit is only useful in saving power when
CADC bit is set.
Reset XDFP
0: XDFP running
1: XDFP reset
Reset Chip
0: no action
1: reset active (RESQ pin low)
Software Reset Enable
0: no software reset possible
1: software reset possible
SDA 55xx
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