SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 141

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
Table 3–8: ACQ register description, continued
Micronas
Name
GRDSIGN
ACQFP7
LEOFLI[11:8]
ACQFP8
LEOFLI[7:0]
ACQLP0
DINCR[15:8]
ACQLP1
DINCR[7:0]
ACQLP2
NORM[2:0]
FCSEL[1:0]
Addr
h0006[0]
h0007
h0007[7:4]
h0008
h0007[3:0]
h000D
h000D[7:0]
h000E
h000E[7:0]
h000F
h000F[7:5]
h000F[4:3]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Sync
VS
VS
VS
VS
HS
HS
HS
HS
HS
HS
HS
Sept. 10, 2004; 6251-556-3DS
LINE_PARAMETER
Reset
0
h0000
0
h0000
0
h0000
0
h0000
0
h0000
0
0
Range
0..7
0..7
0..255
0..255
Function
Group delay detector.
0: If group delay distortion has been detected, it was
positive.
1: If group delay distortion has been detected, it was
negative.
(Written to memory by ACQ-interface)
Detection threshold for negative group delay measurement
detection
Detection threshold for positive group delay measurement
detection
Data PLL Frequency Select
Specifies the operating frequency of the D-PLL of the data
slicer.
DINCR = fdata * 2**18 / 40.5 MHz
Data PLL Frequency Select (Low Byte)
(refer to ACQLP0)
Most timing signals are closely related to the actual data
service used. Therefore 3 bits are reserved to specify the
timing for the service used in the actual line. (corresponds
to slicer 1)
NORMService
000TXT
001reserved
010VPS
011WSS
100CC
101reserved
110reserved
111no data service
There are three different framing codes which can be used
for each field. The framing code used for the actual line is
selected with FCSEL (corresponds to slicer 1).
FCSELFC
00FC1
01FC2
10FC3
11No FC-check
0000: a small negative group delay activates detection
...
0111: strong negative group delay is needed to activate
0000: a small positive group delay activates detection
...
0111: strong positive group delay is needed to activate
SDA 55xx
141