SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 38

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.3.4. Enabling Interrupts
Interrupts are enabled through a set of Interrupt
Enable registers (IEN0, IEN1, IEN2, IEN3).
Bits 0 to 5 of the Interrupt Enable registers each indi-
vidually enable/disable a particular interrupt source.
Overall control is provided by bit 7 of IEN0 (EAL).
When EAL is set to ‘0’, all interrupts are disabled:
when EAL is set to ‘1’, interrupts are individually
enabled or disabled through the other bits of the Inter-
rupt Enable Registers. EAL may however be overrid-
den by the DISINT signal which provides a global dis-
able signal for the interrupt controller.
2.3.4.1. Interrupt Enable Registers (IEN0, IEN1,
The microcontroller has 4 Interrupt Enable registers.
For each bit in these registers, a ‘1’ enables the corre-
sponding interrupt and a ‘0’ disables it.See Table 2–
17.
Table 2–17: Interrupt enable registers
Table 2–18: Interrupt source registers
38
Register Name
IEN0
IEN1
IEN2
IEN3
See Section 3. on page 110 for detailed register description.
Register Name
CISR0
bit addressable
CISR1
it addressable
See Section 3. on page 110 for detailed register description.
IEN2, IEN3)
7
EAL
7
L24
CC
6
Reserved
6
ADC
ADW
5
EAD
EDV
EDH
EADW
5
WTmr
Sept. 10, 2004; 6251-556-3DS
4
EU
EAV
EAH
E24
4
AVS
2.3.5. Interrupt Source Registers
All the interrupts except for timer0, timer1, external
interrupt0, external interrupt1, external extra interrupt0
and external extra interrupt1 are generated by the
respective blocks and are positive edge triggered.
They are sampled in a central interrupt source register,
the corresponding bit must be cleared by the software
after entering the interrupt service routine.
Bit Name
Bit Name
3
ET1
EXX1
ECC
EX21
3
DVS
2
EX1
EWT
EPW
EX20
2
PWtmr
1
ET0
EXX0
EX13
EX19
1
AHS
IEX1
DATA SHEET
0
EX0
EX6
EX12
EX18
0
DHS
IEX0
Micronas