SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 56

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
2.8.3.6. Normal Capture Mode
Normal capture mode is started by setting the RUN bit
(0 --> 1) and PLG = 0, start = 0. Setting RUN bit will
reload the counter with reload value and reset the
overflow bit and counter will start to count.
Upon event on the selected port pin, contents of the
counter are copied to the capture registers CRT_caph
and CRT_capl.
In capture mode if REL bit is set counter is automati-
cally reloaded upon occurrence of the event with the
reload value and starts to count. If however REL bit is
not set then the counter continues to count from the
current value.
OV bit is not effected by the capture event.
Note: Min_cap register has no functionality in this
2.8.3.7. Polling Mode
The polling mode is started by setting the PLG bit to ’1’
(START bit is in don’t care for this mode). Setting the
RUN bit will reload the counter with the reload value
and reset the overflow bit and start the counting.
In the timer polling mode, the capture register mirrors
the current timer value, note that in this mode any
event at the selected port pin is ignored. Upon overflow
the OV bit is set.
Note: Interrupts are not generated as events are not
2.8.3.8. Capture Mode with Spike Suppression at
This mode is specially been implemented to prevent
false interrupt from being generated specially in idle
mode while waiting for a new infrared telegram.
This mode is entered by setting the START bit
(PLG = 0). The software sets the Start bit to indicate it
is expecting a new telegram. Setting the RUN bit will
reload the counter with the reload value and reset the
overflow bit and start the counting.
56
mode.
Interrupt would be generated from CRT, how-
ever it will only be registered in the int source
register if Intsrc bits in the CSCR1 are appropri-
ately set. It is not required to use the CRT gen-
erated interrupt in this mode. Direct pin interrupt
can be used.
recognized.
the Start of an Infrared Telegram
Sept. 10, 2004; 6251-556-3DS
2.8.3.9. First Event
On occurrence of the capture event, the counter value
is captured and the comparator then sets the First bit.
The Interrupt is suppressed. The OV bit is reset and
the counter reloads the reload value (regardless of the
status of REL bit) and starts counting again.
2.8.3.10. Second Event
On occurrence of second capture event, the counter
value is captured and the interrupt is triggered if the
capture value exceeds the value in the Min_Cap regis-
ter and the OV bit is not set. First bit is reset. The
counter will now continue in the normal capture mode.
Software may reset the START bit if the capture value
is detected as a valid pulse of an IR telegram.
If the pulse was invalid then software must stop the
counter and start again (Run bit & First reset and then
SET) with start bit set to wait for a new telegram.
If Capture value is less then or equal to min_cap value
or OV bit has been set, that is spike has been detected
and Interrupt is suppressed. OV bit would be reset
counter would be reloaded with reload value (regard-
less of REL bit).
In this case if either RISE or FALL bit were set then
counter will wait for the second event (First = 1), if
RISE and FALL both were set then counter will wait for
the first event (First = 0).
2.8.3.11. Capture Reload TImer CRT Interrupt
The Capture Reload Timer CRT can generate an inter-
rupt if the Spice Suppression Unit SSU is employed.
The CRT unit uses the same interrupt line as INT1 and
INT0. The interrupt line is selected by the SEL bit.
Note that when using CRT to generate an interrupt, the
direct interrupt source from Port 3.2 or 3.3 (which ever
is
(CSCR1(IntSrc0), CSCR1(IntSrc1)). If the application
uses port pins directly to generate interrupts, then
these bits should be reset. Note that by default INT1
and INT0 are mapped to P3.3 and P3.2.
The SSU generates an interrupt signal as a pulse,
which is captured in the interrupt source register
TCON (IE1 or IE0). While using this mode TCON (IT0
or IT1) must be set to 1 (edge triggered) and IRCON
(EX1R or EX0R) must be set to 1 and IRCON(EX1F or
EX0F) must be set to 0.
For further information on interrupts please refer to
Section 2.3. on page 37.
selected)
should
be
switched
DATA SHEET
to
Micronas
CRT