SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 61

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.9.6. Power-Down, Idle and Power-save Mode
In idle mode the pulse width modulation unit PWMU
continues to function normally, unless it has been
explicitly shut down by PSAVE(PERI). Note that in
PSAVE mode all channels are frozen and the pins are
switched to port output mode making it possible to use
the port lines.
In power-down mode the pulse width modulation unit
PWMU is shut off.
2.9.7. Timer
The pulse width modulation unit PWM unit uses a sin-
gle 14 bit timer to generate signals for all 8 channels.
The timer is mapped into the SFR address space and
hence is readable by the controller. Timer is enabled
(running) if one of the PWM channels is enabled in
PWME. If all the channels are disabled counter is
stopped. Enabling one of the channels will reset the
timer to 0 and start. Note that this reset is done for the
first enabled channel. All other channels enabled later
will drive the output from the current value of the
counter.
If all the channels are disabled then it can be used as a
general purpose timer, by enabling it with PWM_Tmr
bit in PWCH.
Setting PWM_Tmr bit switches to timer mode and
starts the timer. The timer always starts from a reset
value of 0 (OV also reset to 0). Timer can be stopped
any time by turning off the PWM_Tmr bit.
If the timer overflows it sets an over flow bit OV (bit 6)
PWCH and interrupt bit CISR0 (PWtmr) in the central
interrupt register. If the corresponding interrupt enable
bit IEN2(EPW) is set the interrupt will be serviced. OV
bit and PWtmr bits must be reset by the software.
Note: Before utilizing the timer for PWM channels
Micronas
PWM_Tmr bit must be reset.
On reset the CISR0 (PWtmr) bit is initialized to
0, however if the counter overflows this bit might
be set along with OV bit. However clearing OV
bit does not clear the CISR0 (PWtmr) bit. There-
fore the software must clear this bit before
enabling the corresponding interrupt.
Sept. 10, 2004; 6251-556-3DS
SDA 55xx
61