SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 23

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.2.8.3.1. Register Addressing
Register addressing accesses the eight working regis-
ters (R0 … R7) of the selected register bank. The
PSW register flags RS1 and RS0 determine which reg-
ister bank is enabled. The least significant three bits of
the instruction opcode indicate which register is to be
used. ACC, B, DPTR and CY, the Boolean processor
accumulator, can also be addressed as registers.
2.2.8.3.2. Direct Addressing
Direct Byte addressing specifies an on-chip RAM loca-
tion (only low part) or a special function register. Direct
addressing is the only method of accessing the special
function registers. An additional Byte is appended to
the instruction opcode to provide the memory location
address. The highest order bit of this Byte selects one
of two groups of addresses: Values between
00
ues between 80
function registers.
2.2.8.3.3. Register Indirect Addressing
Register indirect addressing uses the contents of
either R0 or R1 (in the selected register bank) as a
pointer to locations in the 256 Bytes of internal RAM.
Note that the special function registers are not acces-
sible by this method.
Execution of PUSH and POP instructions also use reg-
ister-indirect addressing. The stack pointer may reside
anywhere in internal RAM.
2.2.8.3.4. Immediate Addressing
Immediate addressing allows constants to be part of
the opcode instruction in program memory.
An additional Byte is appended to the instruction to
hold the source variable. In the assembly language
and instruction set, a number sign (#) precedes the
value to be used, which may refer to a constant, an
expression, or a symbolic name.
2.2.8.3.5. Base Register plus Index Register Indi-
Base register plus index register indirect addressing
allows a Byte to be accessed from program memory
via an indirect move from the location whose address
is the sum of a base register (DPTR or PC) and index
register, ACC. This mode facilitates accessing to look-
up table resident in program memory.
Micronas
H
… 7F
H
rect Addressing
access internal RAM locations, while val-
H
… 0FF
H
access one of the special
Sept. 10, 2004; 6251-556-3DS
2.2.9. Ports and I/O-Pins
There are 34 Port pins available, out of which 24 are I/
O pins configured as three 8-bit wide ports P0, P1, and
P3. Port 4 consists of 6 I/O bits, out of which only 3 are
available in the PSDIP52-2 package. All 6 port pins are
only available in the other packages with higher pin
count. Each pin can be individually and independently
programmed as input or output and each can be con-
figured dynamically. One 4-bit-port P2 is input only.
An instruction that uses a port's bit/Byte as a source
operand reads a value that is the logical AND of the
last value written to the bit/Byte and the polarity being
applied to the pin/pins by an external device (this
assumes that none of the microcontroller's electrical
specifications are being violated).
An instruction that reads a bit/Byte, operates on the
content, and writes the result back to the bit/Byte,
reads the last value written to the bit/Byte instead of
the logic level at the pin/pins.
Pins of a single port can be individually configured as
inputs and outputs by writing a ‘one’ to each pin that is
to be an input. Each time an instruction uses a com-
plete port as destination, the SW has to make sure that
‘ones’ are written to those bits that correspond to the
pins used as inputs. An external input signal to a port
pin needs not to be synchronized to the internal clock.
All the port latches have ‘one’ s written to them by the
reset function. If a ‘zero’ is subsequently written to a
port latch, it can be reconfigured as an input by writing
a ‘one’ to it.
The instructions that perform a read of, operation on,
and write to a port’s bit/Bytes are INC, DEC, CPL, JBC,
SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and
XRL. The data read by these instructions is the last
value that was written to the port, without regard to the
levels being applied at the pins. This insures that bits
written to a ‘one’ (for use as inputs) are not inadvert-
ently cleared.
Port 0 has an open-drain output. Writing a ‘one’ to the
bit latch leaves the output transistor off, so the pin
floats.
In that condition it can be used as a high-impedance
input. Port 0 is considered ‘true bidirectional’, because
when configured as an input it floats.
Ports 1, 3 and 4 have ‘quasi-bidirectional’ output driv-
ers.
In ports P1, P3 and P4 the output drivers provide
source current for one system clock period if, and only
if, software updates the bit in the output latch from a
‘zero’ to an ‘one’. Sourcing current only on ‘zero to one’
transition prevents a pin, programmed as an input,
SDA 55xx
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