SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 9

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
– ADC (4 channels, 8 bit)
– UART
1.1.3. Memory
– Non-multiplexed 8-bit data and 16…20-bit address
– Memory banking up to 1 MByte (ROMless version)
– Up to 128 kByte on-chip program ROM
– Eight 16-bit data pointer registers (DPTR)
– 256-bytes on-chip processor internal RAM (IRAM)
– 128 bytes extended stack memory
– Display RAM and TXT/VPS/PDC/WSS Data Acqui-
– Up to 16 kByte on-chip extended RAM (XRAM) con-
1.1.4. Display Features
– ROM character set supports all east and west Euro-
– Mosaic graphic character set
– Parallel display attributes
– Single/double width/height of characters
– Variable flash rate
– Programmable screen size
– Flexible character matrixes (H x V) 12 x 9 … 16
– Up to 256 dynamically re-definable characters in
– CLUT with up to 4096 color combinations
– Up to 16 colors per DRCS character
– One out of eight colors for foreground and back-
– Shadowing & contrast reduction
– Pixel by pixel shiftable cursor with up to 4 different
– Support of progressive and 100 Hz double scan
– 3 × 4 bits RGB-DACs on chip
– Free programmable pixel clock from 10 MHz to
Micronas
• 1 kByte on-chip ACQ buffer RAM (access via
• 1 kByte on-chip extended RAM (XRAM, access via
• 3 kByte display memory
bus (ROMless version)
sition Buffer directly accessible via MOVX command
sisting of
pean languages in a single device
(25 rows × 33 … 64 columns)
standard mode; 1024 dynamically re-definable char-
acters in enhanced mode
ground colors for 1-bit DRCS and ROM characters
colors
32 MHz
MOVX)
MOVX) for user software
Sept. 10, 2004; 6251-556-3DS
– Pixel clock independent from CPU clock
– Multinorm H/V-display synchronization in master or
1.1.5. Acquisition Features
– Multistandard digital data slicer
– Parallel multinorm slicing (TTX, VPS, WSS, CC, G+)
– Four different framing codes available
– Data caption only limited by available memory
– Programmable VBI-buffer
– Full channel data slicing supported
– Fully digital signal processing
– Noise measurement and controlled noise compen-
– Attenuation measurement and compensation
– Group delay measurement and compensation
– Exact decoding of echo disturbed signals
1.1.6. Ports
– One 8-bit I/O-port with open drain output and
– Two 8-bit multifunction I/O-ports (Port 1, Port 3)
– One 4-bit port working as digital or analog inputs for
– One 2-bit I/O-port with secondary functions (P4.2,
– One 4-bit I/O-port with secondary function (P4.0,
Fig. 1–1: Logic Symbol
COR_BLA
HSYNC
VSYNC
CVBSO
CVBSI
STOP
XTAL1
XTAL2
slave mode
sation
optional I
the ADC (Port 2)
4.3, 4.7)
4.1, 4.4) Not available in PSDIP52-2)
CVBS
PSEN
ENE
OCF
ALE
RST
WR
RD
R
G
B
2
v
C bus emulation support (Port 0)
cc
TVT PRO
v
ss
Port 0
Port 1
Port 2
Port 3
Port 4
Address
20 bit
Data
8 bit
8 bit
8 bit
4 bit
6 bit
6 bit
SDA 55xx
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