SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 53

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.7. General Purpose Timers/Counters
Two independent general purpose 16-bit timer/
counters are integrated for use to measure time inter-
vals, pulse widths, counting events, and causing peri-
odic (repetitive) interrupts. Both can be configured to
operate as timer or event counter.
In the ‘timer’ function, the registers TLx and/or THx
(x = 0, 1) are incremented once every machine cycle.
As one machine cycle has a length of 12 cycles of the
oscillator the counting frequency is fcrystal /12.
In the ‘counter’ function, the registers TLx and/or THx
(x = 0, 1) are incremented in response to a 1-to-0 tran-
sition at its corresponding external input pin, T0 or T1.
In this function, the external input is sampled during
every machine cycle. If the samples taken show a ‘1’ in
one cycle and a ‘0’ in the next cycle, the count is incre-
mented. The new count value appears in the register
during the cycle following the one in which the transi-
tion was detected. Since it takes 2 machine cycles
(24 oscillator periods) to recognize a ‘1’-to-’0’ transi-
tion, the maximum count rate is 1/24 of the oscillator
frequency. There are no restrictions on the duty cycle
of the external input signal, but to ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
2.7.1. Timer/Counter 0: Mode Selection
Timer/counter 0 can be configured in one of four oper-
ating modes, which are selected by bit-pairs (M1, M0)
in TMOD register. See Section 2.7.1. on page 53.
2.7.1.1. Mode 0
Putting timer/counter 0 into mode 0 makes it looks like
an 8048 timer, which is an 8-bit counter with a divide-
by-32 prescaler. Table 2–32 shows the mode 0 opera-
tion as it applies to timer 0.
In this mode, the timer register is configured as a 13-bit
register. As the count rolls over from all ‘1’ to all ‘0’, it
sets the timer interrupt flag TF0. The timer input is
enabled if TR0 = 1 and either GATE = 0 or INT0 = 1.
(Setting GATE = 1 allows the timer to be controlled by
external input INT0, to facilitate pulse width measure-
ments.) TR0 is a control bit in the special function reg-
ister TCON (see Section 2.8.5. on page 57). GATE is
contained in register TMOD (see Section 2.7.4. on
page 54).
The 13-bit register consists of all 8 bits of TH0 and the
lower 5 bits of TL0. The upper 3 bits of TL0 are not
valid and should be ignored. Setting the run flag TR0
does not clear the registers.
Micronas
Sept. 10, 2004; 6251-556-3DS
2.7.1.2. Mode 1
Mode 1 is the same as mode 0, except that all 16 bits
of the timer/counter 0 register are being used.
2.7.1.3. Mode 2
Mode 2 configures the timer/counter 0 register as an
8-bit counter TL0 with automatic reload. The High Byte
THo is used as storage for the Reload value. Overflow
from TL0 not only sets TF0, but also reloads TL0 with
the contents of TH0, which is preset by software. The
reload leaves TH0 unchanged.
2.7.1.4. Mode 3
Timer/counter 0 in mode 3 establishes TL0 and TH0
as two separate counters. TL0 uses the timer 0 control
bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked
into a timer function (counting machine cycles) and
takes over the use of TR1 and TF1 from timer 1. Thus,
TH0 now controls the ‘timer 1’ interrupt.
Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With timer 0 in mode 3, the
microcontroller can operate as if it has three timers/
counters. When timer 0 is in mode 3, timer 1 can be
turned on and off by switching it out of and into its own
mode 3, or can still be used in any application not
requiring an interrupt.
2.7.2. Timer/Counter 1: Mode Selection
Timer/counter 1 can also be configured in one of four
modes, which are selected by its own bitpairs (M1,
M0) in TMOD register.
The serial port receives a pulse each time that timer/
counter 1 overflows. This pulse rate is divided to gen-
erate the transmission rate of the serial port.
Modes 0 and 1 are the same as for counter 0.
2.7.2.1. Mode 2
The ‘reload’ mode is reserved to determine the fre-
quency of the serial clock signal (not implemented).
2.7.2.2. Mode 3
When counter 1's mode is reprogrammed to mode 3
(from mode 0, 1 or 2), it disables the increment
counter. This mode is provided as an alternative to
using the TR1 bit (in TCON register) to start and stop
timer/counter 1.
SDA 55xx
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