SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 41

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.3.8. Interrupt and Memory Extension
When an interrupt occurs, the Memory Management
Unit (MMU) carries out the following sequence of
actions:
1. The MEX1 register bits are made available on
SDATAO[7:0].
2. The MEXSP register bits are made available on
SADD[7:0].
3. The Stack read and write signals are set for a write
operation.
4. A write is performed to External memory.
5. The MEXSP Stack Pointer is incremented.
6. The Interrupt Bank bits IB19 - IB16 (MEX2.3 -
MEX2.0) are copied to both the NB19 - NB16 and the
CB19 - CB16 bits in the MEX1.
Then on return from the interrupt service routine:
1. The MEXSP Stack Pointer is decremented.
2. The MEXSP register bits are made available on
SADD [7:0].
3. The Stack read and write signals are set for a read
operation.
4. A read is performed on External memory.
5. SDATAI [7:0] is copied to the MEX1 register.
This action allows the user to place interrupt service
routines on specific banks.
2.3.9. Interrupt Handling
External interrupt0, external interrupt1, timer0, timer1
and UART interrupt are handled as follows:
– Interrupts are sampled at Step5 Phase2 in each
– An interrupt of an equal or higher priority is not cur-
– The polling cycle is not the final cycle of a multi-
– The current instruction is neither a RETI nor a write
Micronas
machine cycle and the sampled interrupt informa-
tion is polled during the following machine cycle. If
an interrupt is active when it is sampled, it will be
serviced provided:
rently being serviced.
cycle instruction, and
either to one of Interrupt Enable registers or to one
of the Interrupt Priority registers.
Sept. 10, 2004; 6251-556-3DS
Note: Active interrupts are only stored for one
For all other interrupts the interrupt request is stored
as an interrupt flag in registers CISR0 and CISR1.
These request bits must be cleared by user software
while servicing the interrupt. The interrupts always get
serviced once raised regardless of the number of poll-
ing cycles required to service them.
2.3.10. Interrupt Latency
The response time in a single interrupt system is
between 3 and 9 machine cycles.
2.3.11. Interrupt Flag Clear
In case of external interrupt0 and external interrupt1, if
the external interrupts are edge triggered, the interrupt
flag is cleared when entering into the interrupt service
routine but if they are level triggered, the flag follows
the signal applied to the port pin. Timer/counter flags
are cleared when entering into the interrupt service
routine. All other interrupt flags, including IEX0 and
IEX1 are not cleared by hardware. They must be
cleared by software.
2.3.12. Interrupt Return
For the proper operation of the interrupt controller it is
necessary that all interrupt routines end with a RETI
instruction.
machine cycle. As a result, if an interrupt was
active for one or more polling cycles but not ser-
viced for one of the reasons given above, the
interrupt will not be processed.
SDA 55xx
41