SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 134

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
134
Name
VSU2[3:0]
VL[9:8]
VLR0
VL[7:0]
HPR1
HPR[11:8]
HPR0
HPR[7:0]
Sub
hEE[5:2]
hEE[1:0]
hEF
hEF[7:0]
hF1
hF1[3:0]
hF2
hF2[7:0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
2
h71
113
h08
8
h55
85
Sept. 10, 2004; 6251-556-3DS
0..15
Range
0..3
0..255
0..15
0..255
Function
Vertical Set Up Time 2 (slave mode only)
To realize the odd/even detection of a field next to VSU a second
vertical setup time VSU2 is defined by the VSU2 register bits. This
horizontal delay is used to recognize the VSYNC to another time than
it is recognized at VSU. The field detection is realized by detecting if in
between these two latching-points the VSync is rising or stable:
tV_delay2 = 3.84 us * VSU2
If VSYNC became active for both VSU and VSU2, an odd field is
detected. If VSYNC became active only for VSU an even field is
detected:
with inverted VSU and VSU2:
DSync Vetical line 1
DSync Vertical Line 0
Amount of Vertical Lines in a Frame (master mode only)
TVT generates in sync master mode vertical sync impulses. If for
example a normal PAL timing should be generated, set this register to
“625d” and set the interlace bit to “0”. The hardware will generate a
vertical impulse periodically after 312.5 lines. If a non-interlace picture
with 312 lines should be generated, set this register to “312” and set
the interlace bit to “1”. The hardware will generate a vertical impulse
every 312 lines. A progressive timing can be generated by setting VLR
to “625” and interlace to “0”.
DSync Horizontal Period 1
Horizontal Period Factor (master mode only)
This register allows to adjust the period of the horizontal sync signal.
The horizontal period is independent from the pixel frequency and can
be adjusted with the following resolution:
tH-period = HP x 30 ns
DSync Horizontal Period 0
Horizontal Period Factor (master mode only)
This register allows to adjust the period of the horizontal sync signal.
The horizontal period is independent from the pixel frequency and can
be adjusted with the following resolution:
tH-period = HP x 30 ns
V
field
H
Generated field signal bei utilization of VSU and VSU2
V
field
H
Generated field signal bei utilization of VSU and VSU2
VSU
VSU2
VSU2
VSU
VSU
VSU2
................
................
................
................
................
VSU2
VSU
VSU
VSU2
DATA SHEET
Micronas