SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 63

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.10. Watchdog Timer
The Watchdog timer is a 16 bit up counter which can
be programed to clock by f
count value of the watchdog timer is contained in the
watchdog timer register WDT_high and WDT_low.
which are read-only register. Control and refresh func-
tion of the WDT are controlled by WDT_refresh and
WDT_ctrl.
Additionally the counter can be used as a general pur-
pose timer in timer mode. The associated load register
can be used either as load register or independently as
a scratch pad register by the user.
2.10.1. Input Clock
The input clock f
divided by 12 (i.e. machine cycle). It is fed to the WDT
either as divide-by-2 or divide-by-128 clock signal. The
divider factor is determined by WDT_in (WDT_ctrl)
equal 0 and 1 respectively. WDT_in has the same
functionality in both watch dog mode and timer mode.
2.10.2. Starting
The watch dog timer WDT can be started if the WDT
unit is in the Watch dog mode (WDT_tmr = 0).
WDT is started by setting the bit WDT_start in the
WDT_ctrl register. Immediately after the start (1 clock
cycle) the reload value from the WDT_rel register is
copied to the WDT_high. WDT_low is always reset to
0 upon start.
Data can be written to WDT_rel any time during nor-
mal controller operation. Data are only loaded to the
counter upon start, refresh or watchdog reset (if
WDT_narst is set).
Note that the counter registers are read only and can-
not be directly written to by the controller.
2.10.3. Refresh
Once the watch dog timer WDT is started it cannot be
stopped by software. (Note that while the WDT is run-
ning any change to WDT_tmr bit would be ignored.) A
refresh to the WDT is required before the counter over-
flows. Refreshing the WDT requires two instruction
sequences whereby first instruction sets WDT_ref bit
and the next instruction sets the WDT_start bit. (For
example if there is a NOP between these two instruc-
tions, a refresh would be ignored). This double instruc-
tion refresh minimize the chances of an unintentional
reset of the watchdog timer. Once set, the WDT_ref bit
is reset by the hardware after three machine cycles.
Micronas
wdt
is the same as the CPU clock f
wdt
/2 or f
wdt/
128. The current
Sept. 10, 2004; 6251-556-3DS
sys
A refresh causes WDT_low to reset to 00
the reload value to from WDT_rel to WDT_high.
2.10.4. WDT Reset
If the software fails to refresh the WDT before the
counter overflows after FFFF
watchdog reset is performed.
The watchdog timer reset differs only from the normal
reset in that during normal reset all the WDT relevant
bits in the three registers WDT_rel, WDT_refresh,
WDT_control are reset to 00
tialized to 0000
In case of a watchdog reset, WDT_start and
WDT_narst are not reset. The bit WDT_rst (read only)
is set to indicate the source of the reset. In addition the
WDT reset does not reset the PLL and clock genera-
tor.
If the WDT_narst bit is set then the values in the
WDT_rel are retained after the WDT reset. The
counter starts with the same pre-scaler (WDT_in) and
reload configuration as before reset. If WDT_narst is
not set then upon watchdog reset, WDT_rel is reset to
00h and WDT_in to 0.
After the WDT reset the counter starts again and must
be refreshed by the microcontroller in order to avoid
further WDT resets.
Duration of the WDT reset is sufficient to ensure the
proper reset sequence.
2.10.5. Power-down Mode
The WDT is shut off during power down mode along
with the rest of the peripherals.
In idle mode the WDT (in watchdog mode) is frozen, in
timer mode it continues it’s operation. In power save
mode PSAVE (PERI) the watchdog continues it’s oper-
ation. Any write access to this bit is ignored. If in timer
mode the timer can be frozen by setting this bit.
2.10.6. Time Period
The period between refreshing the watchdog timer and
the next overflow can be determined by the following
formula.
PWDT = [2(1 + (WDT_in) × 6) × (216 - (WDT_rel) ×
28)] / [FWDT]
Based on 33.33 MHz system clock minimum time
period and maximum time period are as defined below.
H
.
H
, an internally generated
H
. The counter gets ini-
SDA 55xx
H
and loads
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