SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 55

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
2.8. Capture Reload Timer
The capture control timer is a 16 bit up counter, with
special features suited for easier infrared decoding by
measuring the time interval between two successive
trigger events. Trigger events can be positive, negative
or both edges of a digital input signal (Port 3.2 or 3.3).
A built in Spike Suppression Unit (SSU) can be used
for suppressing pulses with obviously too small or too
long time duration at the beginning of an expected
telegram, thereby relieving the FW of processing cor-
rupted telegrams. This is especially useful in idle
mode.
2.8.1. Input Clock
The input clock is f
clock frequency divided by two. In normal mode the
system frequency is 33.33 MHz (f
and in slow down mode (SD mode) it is 8.33 MHz
(f
PR prescaler bit: when set the input clock is further
divided by 2, setting PR1 divides further by 8.
If the operation is changed to the SD mode the fre-
quency is adjusted accordingly so that maximum time
resolution of 15.73 ms or 251.66 ms is achieved
depending on Prescaler PR bits.
2.8.2. Reset Values
All the eight 8 bit registers CRT_rell, CRT_relh,
CRT_capl,
CRT_mincaph, CRT_con0 and CRT_con1 are reset
to 00
2.8.3. Functional Description
2.8.3.1. Port Pin
Either Port P3.3 or P3.2 can be selected as capture
input via SEL bit. Capture event can be programmed to
occur on rising or falling edge or both using the bits
RISE and FALL bits.
2.8.3.2. Slow Down Mode
SD bit when set, reduces the system frequency to
8.33 MHz. However the clk to the counter has a fix fre-
quency (for a particular prescaler value). This is
achieved by a divide by 4 chain, which divides the
incoming frequency by 4 when SD = 0 and feeds the
incoming signal directly to the counter when SD = 1.
Micronas
CCT
H
= 4.16 MHz).
.
CRT_caph,
CCT
and is same as the system
CCT
CRT_mincapl,
= 16.66 MHz)
Sept. 10, 2004; 6251-556-3DS
2.8.3.3. Run
When the counter is started (RUN), a 16 bit reload
value is automatically loaded into the 16 bit counter.
(Note: REL bit is irrelevant in case of RUN function).
Setting run bit resets the First and OV bit.
All the control bits PR, PLG, REL, RUN, RISE, FALL,
SEL, Start, Int_Src, SD can be changed anytime dur-
ing the operation. These changes take immediate
effect. There is no protected mode when the counter is
running.
2.8.3.4. Overflow
In case no capture event occurs, the counter keeps on
counting till it overflows from FFFF
transition the OV bit is set. After the overflow the
counter keeps on counting. Overflow does not reload
the reload value. Note that the OV bit is set by the
counter and can be reset by software.
2.8.3.5. Modes
There are three different modes in which the counter
can be used.
– Normal Capture mode
– Polling mode
– Capture mode with spike suppression at the start of
Table 2–32: Timer/Counter mode selection
For each change in the mode selection it is recom-
mended to reset the RUN bit (if it is not already at 0),
set the appropriate mode bit and then re-start the
counter by setting the RUN bit again.
For each of the capture modes the event is captured
based on the CRTCON0 (bit RISE) and CRTCON0 (bit
FALL).
Mode
Normal capture mode
Capture mode with spike
suppression
Polling mode
an IR telegram
START
0
1
X
H
SDA 55xx
to 0000
PLG
0
0
1
H.
At this
55