SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 131

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

DATA SHEET
Table 3–4: SFR register description, continued
Micronas
Name
COR_BL
VSU[3:0]
SCR0
RGB_D[1:0]
HP
VP
INT
Sub
hE1[4]
hE1[3:0]
hE2
hE2[7:6]
hE2[5]
hE2[4]
hE2[3]
Dir
RW
RW
RW
RW
RW
RW
RW
Reset
0
h00
0
0
0
0
Sept. 10, 2004; 6251-556-3DS
Range
0..15
0..3
0..1
0..1
0..1
Function
3-Level Contrast Reduction Output
By means of COR_BL the user is able to switch the COR signal to a
three level signal providing BLANK and contrast reduction information
on pin BLANK/COR.
0: Two level signal for contrast reduction.
1: Three level signal;
Three level signal Level0: BLANK off; COR off.
Level1: BLANK off; COR on.
Level2: BLANK on; COR off.
Note: See Section 4.10.3. on page 165 for the detailed specification of
these levels.
Vertical Set Up Time
The vertical sync signal is internally sampled with the next edge of the
horizontal sync edge. The phase relation between V and H differs from
application to application. To guarantee (vertical) jitter free processing
of external sync signals, the vertical sync impulse can be delayed
before it is internally processed. The following formula shows how to
delay the external V-sync before it is internally latched and processed.
tV_delay = 3.84 us * VSU
DSync Control 0
RGB/COR Delay Circuitry
In some applications of our customers the blanking is fed through
other devices before it is used as a signal to control the multiplexing of
video/RGB-mix. These other devices may create a delay of the blank
signal. If no special effort is taken, this delay would create a vertical
band at the beginning and the end of the active blanking zone.
To compensate this, the generated RGB and the COR signals can be
delayed by TVT in reference to the generated blank signal. This delay
is always a multiple of the pixel-frequency from zero delay up to 3
times pixel delay:
00: Zero delay of RGB/COR-output in reference to BLANK-output.
01: One pixel delay of RGB/COR-output in reference to BLANK-
output.
10: Two pixel delay of RGB/COR-output in reference to BLANK-output.
11: Three pixel delay of RGB/COR-output in reference to BLANK-
output.
H-Pin Polarity
This bit defines the polarity of the H pin (master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
V-Pin Polarity
This bit defines the polarity of the V pin (master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
Interlace / Non-interlace
TVT can either generate an interlaced or a non-interlaced timing
(master mode only). Interlaced timing can only be created if VLR is an
odd number.
0: Interlaced timing is generated.
1: Non-interlaced timing is generated.
SDA 55xx
131