SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 120

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
120
Name
PSW
CY
AC
F0
RS[1:0]
OV
F1
P
ACC
A[7:0]
B
B[7:0]
MSIZ
MSIZ[7:0]
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
SBUF
D[7:0]
Sub
hD0
hD0[7]
hD0[6]
hD0[5]
hD0[4:3]
hD0[2]
hD0[1]
hD0[0]
hE0
hE0[7:0]
hF0
hF0[7:0]
hFF
hFF[7:0]
h98
h98[7]
h98[6]
h98[5]
h98[4]
h98[3]
h98[2]
h98[1]
h98[0]
h99
h99[7:0]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
0
0
0
0
0
0
0
h00
0
h00
0
h0F
15
h00
0
0
0
0
0
0
0
0
h00
0
Sept. 10, 2004; 6251-556-3DS
Range
0..1
0..1
0..1
0..3
0..1
0..1
0..1
0..255
0..255
0..255
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..1
0..255
UART
Function
Program Status Word
Program Status Word
Program Status Word
Program Status Word
Program Status Word
Program Status Word
Program Status Word
Program Status Word
Accumulator
Accumulator
B Register
B register
Scratch Pad Register
Scratch Pad Register
Serial Control
Serial Control
Serial Control
Enables the multiprocessor communication feature in modes 2 and 3.
In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the
received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In mode 0, SM2
should be 0.
Enables serial reception. Set by software to enable reception. Cleared
by software to disable reception.
Is the 9th data bit that will be transmitted in modes 2 and 3. Set or
cleared by software as desired.
In modes 2 and 3, is the 9th data bit that was received. In mode 1, if
SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not
used.
Is the transmit interrupt flag. Set by hardware at the end of the 8th bit
time in mode 0, or at the beginning of the stop bit in the other modes,
in any serial transmission. Must be cleared by software.
Is the receive interrupt flag. Set by hardware at the end of the 8th bit
time in mode 0, or halfway through stop bit time in the other modes, in
any serial reception. Must be cleared by software.
Serial Data Buffer
DATA SHEET
Micronas