DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 108

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

10.
Fourteen address bits are used to control the settings of the registers. The registers control functions of the
framers, LIUs, and BERTs within the DS26519. The map is divided into 16 framers, followed by 16 LIUs and 16
BERTs. Global registers (applicable to all 16 transceivers and BERTs) are located within the address space of
Framer 1.
The register details are provided in the following tables. The framer registers bits are provided for Framer 1 and
address bits A[13:8] determine the framer addressed.
10.1
The framer registers have an offset of 200 hex, the LIU registers have an offset of 20 hex, and the BERT registers
have an offset of 10 hex for each transceiver.
Table 10-1. Register Address Ranges (in Hex)
CHANNEL
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
—
—
DEVICE REGISTERS
Register Listings
00F0–00FF
20F0–20FF
GLOBAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0C00–0CEF
2C00–2CEF
0A00–0AEF
0E00–0EEF
2A00–2AEF
2E00–2EEF
0000–00EF
0200–02EF
0400–04EF
0600–06EF
0800–08EF
2000–20EF
2200–22EF
2400–24EF
2600–26EF
2800–28EF
RECEIVE
FRAMER
—
—
108 of 310
2D00–2DEF
0B00–0BEF
0D00–0DEF
2B00–2BEF
TRANSMIT
0100–01EF
0300–03EF
0500–05EF
0700–07EF
0900–09EF
0F00–0FEF
2100–21EF
2300–23EF
2500–25EF
2700–27EF
2900–29EF
2F00–2FEF
FRAMER
—
—
DS26519 16-Port T1/E1/J1 Transceiver
10C0–10DF
30C0–30DF
10A0–10BF
30A0–30BF
10E0–10FF
30E0–30FF
1000–101F
1020–103F
1040–105F
1060–107F
1080–109F
3000–301F
3020–303F
3040–305F
3060–307F
3080–309F
LIU
—
—
1100–110F
1110–111F
1120–112F
1130–113F
1140–114F
1150–115F
1160–116F
1170–117F
3100–310F
3110–311F
3120–312F
3130–313F
3140–314F
3150–315F
3160–316F
3170–317F
BERT
—
—