DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 2

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

1.
2.
3.
4.
5.
6.
7.
8.
9.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
8.1
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.1.1
9.1.2
9.2.1
9.2.2
9.4.1
9.5.1
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
DETAILED DESCRIPTION.................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
MAJOR OPERATING MODES.........................................................................................17
BLOCK DIAGRAMS.........................................................................................................18
PIN DESCRIPTIONS ........................................................................................................20
FUNCTIONAL DESCRIPTION .........................................................................................33
G
L
C
J
F
S
HDLC C
T
M
P
P
C
R
I
G
P
D
S
F
NITIALIZATION AND
ITTER
INE
RAMER
EST AND
RAMERS
YSTEM
IN
ROCESSOR
ER
YSTEM
LOCK
LOCK
ESETS AND
EVICE
ENERAL
LOBAL
ICROCONTROLLER
S
LAVE
F
SPI Serial Port Mode............................................................................................................................ 33
SPI Functional Timing Diagrams ......................................................................................................... 33
Backplane Clock Generation ............................................................................................................... 35
CLKO Output Clock Generation........................................................................................................... 37
Example Device Initialization and Sequence ....................................................................................... 39
General-Purpose I/O Pins .................................................................................................................... 40
-P
Elastic Stores ....................................................................................................................................... 43
IBO Multiplexing ................................................................................................................................... 46
H.100 (CT Bus) Compatibility .............................................................................................................. 55
Transmit and Receive Channel Blocking Registers............................................................................. 57
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 57
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 57
T1 Framing........................................................................................................................................... 58
E1 Framing........................................................................................................................................... 61
T1 Transmit Synchronizer .................................................................................................................... 63
Signaling .............................................................................................................................................. 64
T1 Data Link......................................................................................................................................... 69
E1 Data Link......................................................................................................................................... 71
I
UNCTIONAL
NTERFACE
ORT
A
S
S
I
/F
R
I
ONTROLLERS
NTERRUPTS
B
TTENUATOR
YNTHESIZERS
TRUCTURE
S
NTERFACE
......................................................................................................................................10
......................................................................................................................................58
ESOURCES
D
ACKPLANE
ORMATTER
ERIAL
R
IAGNOSTICS
ESOURCES
I
P
NTERFACE
OWER
............................................................................................................................10
P
D
ERIPHERAL
ESCRIPTION
C
.......................................................................................................................35
......................................................................................................................11
P
-D
.....................................................................................................................10
.....................................................................................................................41
ONFIGURATION
I
....................................................................................................................11
....................................................................................................................40
NTERFACE
ARALLEL
...................................................................................................................12
..................................................................................................................10
OWN
................................................................................................................12
................................................................................................................33
................................................................................................................40
M
I
ODES
NTERFACE
......................................................................................................20
TABLE OF CONTENTS
P
ORT
...................................................................................................43
..............................................................................................38
..............................................................................................39
.............................................................................................12
(SPI) F
2 of 310
EATURES
............................................................12
DS26519 16-Port T1/E1/J1 Transceiver