DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 139

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Channels:
Bit #
Name
Default
Bit 6: RSYSCLKn Select (RSYSCLKSEL)
Bit 5: TSYSCLKn Select (TSYSCLKSEL)
Bit 4: TCLKn Select (TCLKSEL)
Bits 3 to 0: Clock Out Frequency Select (CLKOSEL[3:0]). CLKO output pin will use MCLK (1.544MHz or
2.048MHz or scaled version) as its reference. The following table shows how to configure for each frequency. For
best jitter performance use a 2.048MHz oscillator for MCLK.
CLKOSEL[3:0]
0 = Use RSYSCLKn pins for each receive system clock (Channels 1–8).
1 = Use BPCLK1 as the master clock for all eight receive system clocks (Channels 1–8).
0 = Use TSYSCLKn pins for each transmit system clock (Channels 1–8).
1 = Use BPCLK1 as the master clock for all eight transmit system clocks (Channels 1–8).
0 = Use TCLKn pins for each of the transmit clock (Channels 1–8).
1 = Use REFCLKIO as the master clock for all eight transmit clocks (Channels 1–8).
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
—
7
0
RSYSCLKSEL
GTCCR3
Global Transceiver Clock Control Register 3
00F4h
1 to 8
6
0
CLKO (kHz)
16384
12352
12288
2048
4096
8192
1544
3088
6176
1536
3072
6144
128
256
32
64
TSYSCLKSEL
5
0
TCLKSEL
139 of 310
4
0
CLKOSEL3
3
0
DS26519 16-Port T1/E1/J1 Transceiver
CLKOSEL2
2
0
CLKOSEL1
1
0
CLKOSEL0
0
0