DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 96

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

9.12.2.2
The DS26519 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU Transmit
Impedance and Pulse Shape Selection Register (LTIPSR). This mode also requires a 1μF blocking capacitor
between TTIPn and the transformer. Additionally, the following registers should set to center the pulse to meet the
pulse template:
9.12.2.3
The individual transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control Register
(LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIPn
and TRINGn pins.
When transmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference.
Data input from the framer is ignored. AIS can be sent by setting a bit in the
also be sent if the corresponding receiver goes into LOS state and the ATAIS bit is set in the LMCRl register.
9.12.2.4
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is
approximately 25Ω or less. TSCS (LRSR.2) provides a real-time indication of when the current limiter is activated.
The LIU Latched Status Register (LLSR) provides latched versions of the information, which can be used to
activate an interrupt when enable via the
9.12.2.5
The DS26519 can also detect when the TTIPn or TRINGn outputs are open circuited. OCS (LRSR.1) will provide a
real-time indication of when an open circuit is detected. Register
which can be used to activate an interrupt when enabled via the
not available in T1 CSU operating modes (LBO 5, LBO 6, and LBO 7).
If configuring for E1 120Ω mode, set register addresses 0x1229 = 0xF8 and 0x122D = 0x09.
Transmit G.703 Section 10 Synchronization Signal
Transmit Power-Down
Transmit Short-Circuit Detector/Limiter
Transmit Open-Circuit Detector
If configuring for E1 75Ω mode, set register address 0x1229 = 0xF8.
LSIMR
register.
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LLSR
LSIMR
provides latched versions of the information,
register. The open-circuit-detect feature is
DS26519 16-Port T1/E1/J1 Transceiver
LMCR
register. Transmit all ones will