DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 132
DS26519GA2
Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26519GA2.pdf
(310 pages)
Specifications of DS26519GA2
Part # Aliases
90-26519-0A2
- Current page: 132 of 310
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Register Name
Register Description:
Register Address:
Channels:
Bit #
Name
Default
Bits 7 to 5: General-Purpose I/O Pins Select (GPSEL[3:1]). GPSEL0 must be set to 1 to output this selection.
Table 10-13. DS26519 GPIO Control (9 to 16)
Bit 3: GPIO Select 0 (GPSEL0)
Bit 2: Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an
external “wire-OR” operation. Normally this bit should be set = 0 and the internal mux used.
Note: Setting GIBO disables the internal IBO mux.
configuration.
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must
be cleared and set again to perform another counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI)
GPSEL[3:1]
000
001
010
011
100
101
110
111
0 = GPIO16:9] are inputs.
1 = GPIO[16:9] are outputs selected by GPSEL[3:1].
0 = Use internal IBO mux.
1 = Externally “wire-OR” TSERn and RSERn for IBO operation.
0 = Normal Operation. Interrupt pin ( INTB ) will toggle low on an unmasked interrupt condition.
1 = Interrupt Inhibit. Interrupt pin ( INTB ) is forced high (inactive) when this bit is set.
GPSEL3
7
0
GPIO[16:9] OUTPUT
Logic 0—All 8 GPIOs
Logic 1—All 8 GPIOs
GTCR2
Global Transceiver Control Register 2
20F0h
9 to 16
GPSEL2
Reserved
RSIGFn
RLOFn
LOTCn
FLOSn
ALOSn
6
0
GPSEL1
5
0
132 of 310
GPSEL0
4
0
GFCR2
must be set to inform the framers of the IBO
—
3
0
DS26519 16-Port T1/E1/J1 Transceiver
GIBO
0
2
GCLE
1
0
GIPI
0
0
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