DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 233

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: TCLKn Invert (TCLKINV)
Bit 6: TSYNCn Invert (TSYNCINV)
Bit 5: TSSYNCIOn (Input Mode Only) Invert (TSSYNCINV)
Bit 4: TSYSCLKn Mode Select (TSCLKM)
Bit 3: TSSYNCIOn Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNCIOn pin.
Bit 2: TSYNCn I/O Select (TSIO)
Bit 1: TSYNCn Double-Wide (TSDW) (T1 Mode Only) (Note: This bit must be set to zero when TSM = 1 or when
TSIO = 0.)
Bit 0: TSYNCn Mode Select (TSM). Selects frame or multiframe mode for the TSYNCn pin.
0 = No inversion.
1 = Invert.
0 = No inversion.
1 = Invert.
0 = No inversion.
1 = Invert.
0 = If TSYSCLKn is 1.544MHz.
1 = If TSYSCLKn is 2.048/4.096/8.192MHz or IBO enabled (see Section
0 = Frame mode.
1 = Multiframe mode.
0 = TSYNCn is an input.
1 = TSYNCn is an output.
0 = Do not pulse double-wide in signaling frames.
1 = Do pulse double-wide in signaling frames.
0 = Frame mode.
1 = Multiframe mode.
TCLKINV
TCLKINV
7
0
TSYNCINV
TSYNCINV
TIOCR
Transmit I/O Configuration Register
184h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
6
0
TSSYNCINV
TSSYNCINV
5
0
TSCLKM
TSCLKM
233 of 310
4
0
TSSM
TSSM
3
0
DS26519 16-Port T1/E1/J1 Transceiver
TSIO
TSIO
9.8.2
2
0
for details on IBO function).
TSDW
—
1
0
TSM
TSM
0
0