DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 8

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

DS26519 16-Port T1/E1/J1 Transceiver
Table 10-2. Global Register Mapping ...................................................................................................................... 109
Table 10-3. Global Register List .............................................................................................................................. 109
Table 10-4. Framer Register List ............................................................................................................................. 110
Table 10-5. LIU Register List ................................................................................................................................... 117
Table 10-6. BERT Register List ............................................................................................................................... 117
Table 10-7. Global Register Bit Map........................................................................................................................ 118
Table 10-8. Framer Register Bit Map ...................................................................................................................... 119
Table 10-9. LIU Register Bit Map ............................................................................................................................ 128
Table 10-10. BERT Register Bit Map ...................................................................................................................... 129
Table 10-11. Global Register Set ............................................................................................................................ 130
Table 10-12. DS26519 GPIO Control (1 to 8) ......................................................................................................... 131
Table 10-13. DS26519 GPIO Control (9 to 16) ....................................................................................................... 132
Table 10-14. Master Clock Input Selection.............................................................................................................. 136
Table 10-15. Backplane Reference Clock Select (1 to 8)........................................................................................ 137
Table 10-16. Backplane Reference Clock Select (9 to 16) ..................................................................................... 138
Table 10-17. Device ID Codes in this Product Family ............................................................................................. 142
Table 10-18. LIU Register Set ................................................................................................................................. 250
Table 10-19. Transmit Load Impedance Selection.................................................................................................. 252
Table 10-20. Transmit Pulse Shape Selection ........................................................................................................ 252
Table 10-21. Receive Level Indication .................................................................................................................... 257
Table 10-22. Receive Impedance Selection............................................................................................................ 258
Table 10-23. Receiver Sensitivity Selection with Monitor Mode Disabled............................................................... 259
Table 10-24. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................................... 259
Table 10-25. BERT Register Set ............................................................................................................................. 260
Table 10-26. BERT Pattern Select .......................................................................................................................... 262
Table 10-27. BERT Error Insertion Rate ................................................................................................................. 263
Table 10-28. BERT Repetitive Pattern Length Select ............................................................................................. 263
Table 12-1. Recommended DC Operating Conditions ............................................................................................ 287
Table 12-2. Capacitance.......................................................................................................................................... 287
Table 12-3. Recommended DC Operating Conditions ............................................................................................ 287
Table 12-4. Thermal Characteristics........................................................................................................................ 288
Table 12-5. Transmitter Characteristics................................................................................................................... 288
Table 12-6. Receiver Characteristics....................................................................................................................... 288
Table 13-1. SPI Bus Mode Timing........................................................................................................................... 289
Table 13-2. AC Characteristics—Microprocessor Bus Timing ................................................................................ 291
Table 13-3. Receiver AC Characteristics ................................................................................................................ 294
Table 13-4. Transmit AC Characteristics................................................................................................................. 297
Table 13-5. JTAG Interface Timing.......................................................................................................................... 300
Table 13-6. System Clock AC Characteristics......................................................................................................... 301
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 306
Table 14-2. ID Code Structure................................................................................................................................. 307
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