DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 29

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

SPI_SWAP
SPI_CPHA
SPI_CPOL
SPI_SCLK
SPI_MOSI
SPI_MISO
NAME
RDB /
D[7]/
D[6]/
D[5]/
D[2]/
D[1]/
D[0]/
CSB
DSB
D[4]
D[3]
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C16
A20
G11
A21
A22
H10
B19
H11
D15
G13
B20
AA6
AB5
R14
AA5
P14
PIN
F12
F13
T14
W8
H9
U8
Y9
Y8
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
I
I
MICROPROCESSOR INTERFACE
Address [13:0]. This bus selects a specific register in the DS26519 during
read/write access. A13 is the MSB and A0 is the LSB.
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section
9.1.2
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section
9.1.2
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are
never changed in the control word.
Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [2]/SPI Serial Interface Clock
D[2]: Bit 2 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_SCLK: SPI Serial Clock Input when SPI_SEL = 1.
Data [1]/SPI Serial Interface Data Master Out-Slave In
D[1] : Bit 1 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when CSB = 1.
SPI_MOSI: SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1.
Data [0]/SPI Serial Interface Data Master In-Slave Out
D[0]: Bit 0 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_MISO: SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26519 registers. The DS26519 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received first.
for detailed timing and functionality information. Default setting is low.
for detailed timing and functionality information. Default setting is low.
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FUNCTION
DS26519 16-Port T1/E1/J1 Transceiver