DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 267

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: BERT Bit Error Detected Event (BBED)
Bit 3: BERT Receive All Ones Condition (BRA1)
Bit 2: BERT Receive All Zeros Condition (BRA0)
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS)
Bit 0: BERT in Synchronization Condition (BSYNC)
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
7
0
BSIM
BERT Status Interrupt Mask Register
110Fh + (10h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
BBED
6
0
5
0
267 of 310
4
0
BRA1
3
0
DS26519 16-Port T1/E1/J1 Transceiver
BRA0
2
0
BRLOS
1
0
BSYNC
0
0

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