DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 87

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

9.10.2 Transmit HDLC Controller
9.10.2.1
The Transmit HDLC FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count remains valid and stable during
the read cycle.
9.10.2.2
The HDLC status registers in the DS26519 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
for using the DS26519 HDLC receiver.
FIFO Information
HDLC Transmit Example
87 of 310
DS26519 16-Port T1/E1/J1 Transceiver
Figure 9-19
shows an example routine