DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 263

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the
generated data pattern. Can be used for verifying error detection features. See
Table 10-27. BERT Error Insertion Rate
Bit 4: Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set
again for a subsequent bit error to be inserted.
Bits 3 to 0: Repetitive Pattern Length Select 3 to 0 (RPL[3:0]). RPL0 is the LSB and RPL3 is the MSB of a
nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits
are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns fewer
than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or
equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30
(1101). See
Table 10-28. BERT Repetitive Pattern Length Select
EIB2
0
0
0
0
1
1
1
1
LENGTH
(BITS)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EIB1
0
0
1
1
0
0
1
1
Table
EIB2
7
0
EIB0
0
1
0
1
0
1
0
1
RPL3
10-28.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
No errors automatically inserted
10E-1
10E-2
10E-3
10E-4
10E-5
10E-6
10E-7
BC2
BERT Control Register 2
1106h + (10h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
EIB1
ERROR RATE INSERTED
6
0
RPL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
EIB0
5
0
RPL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
263 of 310
SBE
4
0
RPL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RPL3
3
0
DS26519 16-Port T1/E1/J1 Transceiver
Table
RPL2
2
0
10-27.
RPL1
1
0
RPL0
0
0