DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 252

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit Impedance On (TIMPTON)
Bits 5 and 4: Transmit Load Impedance 1 and 0 (TIMPL[1:0]). These bits are used to select the transmit load
impedance. These must be set to match the cable impedance. Even if the internal load impedance is turned off (via
TIMPTOFF); the external cable impedance has to be specified for optimum operation. For J1 applications, use
110 Ω . See
Bits 2 to 0: Line Build-Out Select 2 to 0 (L[2:0])
voltage level and load impedance associated with it once the T1/J1 or E1 selection is made by settings in the
LTRCR register. See
Table 10-19. Transmit Load Impedance Selection
Table 10-20. Transmit Pulse Shape Selection
L2
L2
Bit 7: Transmit G.703 Synchronization Clock (TG703)
0
0
0
0
0
0
1
1
1
1
TIMPL1
0
0
1
1
L1
L1
0
0
0
0
1
1
0
0
1
1
0 = Normal transmitter mode.
1 = G.703 2.048MHz clock transmitted on TTIPn and TRINGn.
0 = Disable transmit terminating impedance.
1 = Enable transmit terminating impedance.
L0
L0
0
1
0
1
0
1
0
1
0
1
Table
TG703
TIMPLO
7
0
MODE
MODE
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
T1/J1
10-19.
E1
E1
0
1
0
1
Table
TIMPTON
LTIPSR
LIU Transmit Impedance and Pulse Shape Selection Register
1001h + (20h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
DSX-1/0dB CSU, 0ft–133ft ABAM 100 Ω
DSX-1, 133ft–266ft ABAM 100 Ω
DSX-1, 266ft–399ft ABAM 100 Ω
DSX-1, 399ft–533ft ABAM 100 Ω
DSX-1, 533ft–655ft ABAM 100 Ω
-7.5dB CSU
-15dB CSU
-22.5dB CSU
IMPEDANCE
10-20.
6
0
120 Ω
IMPEDANCE SELECTION
75 Ω
CABLE LENGTH
TIMPL1
100 Ω
110 Ω
120 Ω
75 Ω
5
0
VOLTAGE
NOMINAL
2.37V
.
3.0V
Used to select the transmit waveshape. The waveshape has a
TIMPL0
252 of 310
4
0
CABLE LOSS
3
0
ALLOWED
0.6dB
1.2dB
1.8dB
2.4dB
3.0dB
MAX
DS26519 16-Port T1/E1/J1 Transceiver
L2
2
0
L1
1
0
L0
0
0

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