DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 289

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
13.
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
13.1
13.1.1 SPI Bus Mode
Table 13-1. SPI Bus Mode Timing
(See
SYMBOL
(Note 2)
t4, t5
t10
Figure
t1
t2
t3
t6
t7
t8
t9
AC TIMING CHARACTERISTICS
Microprocessor Bus AC Characteristics
The timing parameters in this table are guaranteed by design (GBD).
Symbols refer to dimensions in
100pF load on all SPI pins.
Hold time to high-impedance state.
With 100pF on all SPI pins.
13-1.) (Note 1)
Operating Frequency
Slave
Cycle Time: Slave
Enable Lead Time
Enable Lag Time
Clock (CLK) Duty Cycle
Slave (t4/t1 or t5/t1)
Data Setup Time (Inputs)
Slave
Data Hold Time (Inputs)
Slave
Disable Time, Slave (Note 4)
Data Valid Time, After Enable Edge
Slave (Note 5)
Data Hold Time, Outputs, After Enable Edge
Slave
CHARACTERISTIC (Note 3)
Figure
13-1.
289 of 310
SYMBOL
f
t
t
t
BUS(S)
t
LEAD(S)
CLKH(S)
t
t
t
CYC(S)
LAG(S)
DIS(S)
t
t
SU(S)
HD(S)
DS26519 16-Port T1/E1/J1 Transceiver
H(S)
V(S)
MIN
200
15
15
80
15
5
5
MAX
25
40
5
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns

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