DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 114

IC H8S MCU FLASH 5V 128K 128QFP

DF2357F20

Manufacturer Part Number
DF2357F20
Description
IC H8S MCU FLASH 5V 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2357F20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2357F20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2357F20IV
Manufacturer:
Renesas Electronics America
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Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes
for the interrupt controller.
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
5.2.2
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than
NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 84 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Interrupt Priority Registers A to K (IPRA to IPRK)
Bit 5
INTM1
0
1
Bit 3
NMIEG
0
1
:
:
7
0
Bit 4
INTM0
0
1
0
1
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
IPR6
R/W
6
1
Interrupt
Control Mode
0
2
IPR5
R/W
5
1
IPR4
R/W
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
4
1
3
0
IPR2
R/W
2
1
IPR1
R/W
1
1
IPR0
R/W
0
1
(Initial value)
(Initial value)

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