DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 309

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.3
9.3.1
Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0,
TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered
input.
Figure 9-2 shows the port 2 pin configuration.
9.3.2
Table 9-4 shows the port 2 register configuration.
Table 9-4
Note: * Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR
cannot be read; if it is, an undefined value will be read.
Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an
input pin.
Bit
Initial value :
R/W
Port 2
Overview
Register Configuration
Name
Port 2 data direction register
Port 2 data register
Port 2 register
Port 2 Registers
:
:
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
W
7
0
W
6
0
Port 2
W
5
0
Figure 9-2 Port 2 Pin Functions
Port 2 pins
P2
P2
P2
P2
P2
P2
P2
P2
Abbreviation
P2DDR
P2DR
PORT2
7
6
5
4
3
2
1
0
(I/O)/PO7 (output)/TIOCB5 (I/O)/TMO1 (output)
(I/O)/PO6 (output)/TIOCA5 (I/O)/TMO0 (output)
(I/O)/PO5 (output)/TIOCB4 (I/O)/TMCI1 (input)
(I/O)/PO4 (output)/TIOCA4 (I/O)/TMRI1 (input)
(I/O)/PO3 (output)/TIOCD3 (I/O)/TMCI0 (input)
(I/O)/PO2 (output)/TIOCC3 (I/O)/TMRI0 (input)
(I/O)/PO1 (output)/TIOCB3 (I/O)
(I/O)/PO0 (output)/TIOCA3 (I/O)
W
4
0
W
3
0
R/W
W
R/W
R
W
2
0
Initial Value
H'00
H'00
Undefined
W
Rev.6.00 Oct.28.2004 page 279 of 1016
1
0
W
0
0
Address*
H'FEB1
H'FF61
H'FF51
REJ09B0138-0600H