DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 333

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port A Register (PORTA)
Note: * Determined by state of pins PA
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port
A pins (PA
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed
while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and
PADR are initialized. PORTA retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port A MOS Pull-Up Control Register (PAPCR) (On-Chip ROM Version Only)
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an
individual bit basis.
All the bits are valid in modes 6 and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0
(input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PAPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Bit
Initial value :
R/W
7
to PA
:
:
:
:
:
:
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR
PA7DR
0
R/W
PA7
) must always be performed on PADR.
R/W
—*
7
0
7
R
7
0
PA6DR
R/W
PA6
R/W
—*
6
0
6
R
6
0
PA5DR
7
to PA
R/W
PA5
R/W
—*
5
0
5
R
5
0
0
.
PA4DR
R/W
PA4
R/W
—*
4
0
4
R
4
0
PA3DR
R/W
PA3
R/W
—*
3
0
3
R
3
0
PA2DR
R/W
PA2
R/W
—*
2
0
2
R
2
0
PA1DR
R/W
PA1
R/W
—*
Rev.6.00 Oct.28.2004 page 303 of 1016
1
0
1
R
1
0
7
PA0DR
to PA
R/W
PA0
R/W
—*
0
0
0
R
0
0
0
).
REJ09B0138-0600H