DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 71

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.6.4
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field
(r), an effective address extension (EA), and a condition field (cc).
Figure 2-9 shows examples of instruction formats.
(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on
the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation
fields.
(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits.
Some instructions have two register fields. Some have no register field.
(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
(4) Condition Field: Specifies the branching condition of Bcc instructions.
2.7
2.7.1
The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all
addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct,
register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST
instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Basic Instruction Formats
Addressing Modes and Effective Address Calculation
Addressing Mode
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
op
op
op
Figure 2-9 Instruction Formats (Examples)
cc
EA (disp)
op
rn
rn
EA (disp)
rm
rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
BRA d:16, etc.
Rev.6.00 Oct.28.2004 page 41 of 1016
REJ09B0138-0600H