DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 700

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7,
AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode.
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
21.2.2
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398.
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bits 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be
written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398. Only 0 should be written to this bit.
Bits 4 and 3—Reserved: These bits are always read as 0. Only 0 should be written to these bits.
Rev.6.00 Oct.28.2004 page 670 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
System Clock Control Register (SCKCR)
Bit 3
OPE
0
1
Bit 7
PSTOP
0
1
:
:
PSTOP
R/W
7
0
Normal
Operating Mode
ø output (initial value)
Fixed high
Description
In software standby mode, address bus and bus control signals are high-impedance
In software standby mode, address bus and bus control signals retain output state
R/W
—
6
0
—/(R/W)*
—
5
0
Sleep Mode
ø output
Fixed high
—
—
4
0
Description
—
—
3
0
Software
Standby Mode
Fixed high
Fixed high
SCK2
R/W
2
0
SCK1
R/W
1
0
Hardware
Standby Mode
High impedance
High impedance
SCK0
R/W
0
0
(Initial value)