DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 338

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.9.2
Table 9-15 shows the port B register configuration.
Table 9-15 Port B Registers
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR) (On-Chip ROM Version Only)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR
cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port B Data Register (PBDR) (On-Chip ROM Version Only)
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software
standby mode.
Rev.6.00 Oct.28.2004 page 308 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin
an input port.
Mode 6
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the
pin an input port.
Modes 4 and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Register Configuration (On-Chip ROM Version Only)
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
:
:
:
:
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
PB7DR
R/W
W
7
0
7
0
PB6DR
R/W
W
6
0
6
0
PB5DR
R/W
W
5
0
5
0
PB4DR
R/W
W
4
0
4
0
Abbreviation
PBDDR
PBDR
PORTB
PBPCR
PB3DR
R/W
W
3
0
3
0
PB2DR
R/W
W
R/W
R
R/W
R/W
W
2
0
2
0
Initial Value
H'00
H'00
Undefined
H'00
PB1DR
R/W
W
1
0
1
0
7
PB0DR
to PB
R/W
W
0
0
0
0
0
). PBDR is initialized to
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71