DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 531

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In serial transmission, the SCI operates as described below.
[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
[3] The SCI checks the TDRE flag at the timing for sending the stop bit.
Figure 14-11 shows an example of SCI operation for transmission using the multiprocessor format.
data from TDR to TSR.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
[a] Start bit:
[b] Transmit data:
[c] Multiprocessor bit
[d] Stop bit(s):
[e] Mark state:
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in
which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI)
request is generated.
One 0-bit is output.
8-bit or 7-bit data is output in LSB-first order.
One multiprocessor bit (MPBT value) is output.
One or two 1-bits (stop bits) are output.
1 is output continuously until the start bit that starts the next transmission is sent.
request generated
TDRE
TEND
TXI interrupt
1
Start
bit
0
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Figure 14-11 Example of SCI Operation in Transmission
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt service
routine
D0
D1
1 frame
Data
D7
Multi-
proce-
ssor
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
Rev.6.00 Oct.28.2004 page 501 of 1016
D7
Multi-
proces-
sor bit
0/1
TEI interrupt
request generated
Stop
bit
1
Idle state
(mark state)
1
REJ09B0138-0600H