DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 240

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.5.7
In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be
specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1.
In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this
is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by
MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a
number of bytes or words).
Table 7-11 summarizes register functions in block transfer mode.
Table 7-11 Register Functions in Block Transfer Mode
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Transfer count register A
ETCRB: Transfer count register B
MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits.
MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB.
Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed
(where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB.
Figure 7-13 illustrates operation in block transfer mode when MARB is designated as a block area.
Rev.6.00 Oct.28.2004 page 210 of 1016
REJ09B0138-0600H
Block Transfer Mode
Register
23
23
15
MARA
MARB
ETCRB
7
7
ETCRAH
ETCRAL
0
0
0
0
0
Function
Source address
register
Destination
address register
Holds block
size
Block size
counter
Block transfer
counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Block size
Block size
Number of block
transfers
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000