DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 661

IC H8S MCU FLASH 5V 128K 128QFP

DF2357F20

Manufacturer Part Number
DF2357F20
Description
IC H8S MCU FLASH 5V 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2357F20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2357F20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2357F20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers
(FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be
read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.16.6 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory
programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode. RAMER settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 19-34. To ensure correct operation of the emulation function, the ROM
for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal
execution of an access immediately after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS =
1, all flash memory blocks are program/erase-protected.
Bit
Initial value :
R/W
Bit 3
RAMS
0
1
Bit 3
FLSHE
0
1
:
:
7
0
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Description
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
6
0
5
0
4
0
RAMS
R/W
3
0
RAM2
R/W
2
0
RAM1
R/W
Rev.6.00 Oct.28.2004 page 631 of 1016
1
0
RAM0
R/W
0
0
(Initial value)
(Initial value)
REJ09B0138-0600H

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