DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 214

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block
transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
For operation in normal mode and block transfer mode, see section 7.5, Operation.
Bits 10 to 7—Reserved: Can be read or written to. Write 0 to these bits.
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address
register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 4—Reserved: Can be read or written to. Write 0 to this bit.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The
factors that can be specified differ between normal mode and block transfer mode.
Rev.6.00 Oct.28.2004 page 184 of 1016
REJ09B0138-0600H
Normal Mode
Bit 12
BLKDIR
0
1
Bit 6
DAID
0
1
Bit 3
DTF3
0
1
Bit 2
DTF2
0
1
Bit 11
BLKE
0
1
0
1
Bit 5
DAIDE
0
1
0
1
Bit 1
DTF1
0
1
0
1
Description
Transfer in normal mode
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
Description
MARB is fixed
MARB is incremented after a data transfer
MARB is fixed
MARB is decremented after a data transfer
When DTSZ = 0, MARB is incremented by 1 after a transfer
When DTSZ = 1, MARB is incremented by 2 after a transfer
When DTSZ = 0, MARB is decremented by 1 after a transfer
When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 0
DTF0
0
1
0
1
0
1
Description
—
—
Activated by DREQ pin falling edge input
Activated by DREQ pin low-level input
—
Auto-request (cycle steal)
Auto-request (burst)
—
(Initial value)
(Initial value)
(Initial value)
: Don't care