DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 133

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.1
The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas.
The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling
multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU,
DMA controller (DMAC), and data transfer controller (DTC).
6.1.1
The features of the bus controller are listed below.
Manages external address space in area units
Basic bus interface
DRAM interface
Burst ROM interface
Idle cycle insertion
Write buffer functions
Bus arbitration function
In advanced mode, manages the external space as 8 areas of 2-Mbytes
Bus specifications can be set independently for each area
DRAM/burst ROM interfaces can be set
Chip select (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
DRAM interface can be set for areas 2 to 5 (in advanced mode)
Row address/column address multiplexed output (8/9/10 bits)
Two byte access methods (2-CAS)
Burst operation (fast page mode)
T
Choice of CAS-before-RAS refreshing or self-refreshing
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle
External write cycle and internal access can be executed in parallel
DMAC single-address mode and internal access can be executed in parallel
Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
P
Overview
Features
cycle insertion to secure RAS precharging time
Section 6 Bus Controller
Rev.6.00 Oct.28.2004 page 103 of 1016
REJ09B0138-0600H