DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 529

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.3
The multiprocessor communication function performs serial communication using the multiprocessor format, in which a
multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be
performed among a number of processors sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving
station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle
and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as
data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station
whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data
with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of
processors.
Figure 14-9 shows an example of inter-processor communication using the multiprocessor format.
Data Transfer Format: There are four data transfer formats.
When the multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 14-10.
Clock: See the section on asynchronous mode.
Multiprocessor Communication Function
Figure 14-9 Example of Inter-Processor Communication Using Multiprocessor Format
Serial
data
Legend:
MPB: Multiprocessor bit
Transmitting
Receiving
station A
(ID= 01)
station
(Transmission of Data H'AA to Receiving Station A)
ID transmission cycle=
specification
receiving station
H'01
Receiving
station B
(ID= 02)
(MPB= 1)
Serial transmission line
Data transmission cycle=
Data transmission to
receiving station specified by ID
Receiving
H'AA
station C
(ID= 03)
(MPB= 0)
Rev.6.00 Oct.28.2004 page 499 of 1016
Receiving
station D
(ID= 04)
REJ09B0138-0600H