DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 566

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M = (0.5 –
Where M: Reception margin (%)
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows.
When D = 0.5 and F = 0,
Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
[6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR
Rev.6.00 Oct.28.2004 page 536 of 1016
REJ09B0138-0600H
Retransfer operation when SCI is in receive mode
Figure 15-11 illustrates the retransfer operation when the SCI is in receive mode.
in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0
until the next parity bit is sampled.
normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI
interrupt request is generated.
If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the
RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0.
Retransfer operation when SCI is in transmit mode
Figure 15-12 illustrates the retransfer operation when the SCI is in transmit mode.
is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR
should be kept cleared to 0 until the next parity bit is sampled.
M = (0.5 – 1/2 372) 100%
N: Ratio of bit rate to clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
= 49.866%
2N
1
RDRF
PER
Ds
) – (L – 0.5) F –
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 15-11 Retransfer Operation in SCI Receive Mode
nth transfer frame
D – 0.5
N
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(1 + F
Retransferred frame
100%
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
Transfer
frame n+1