DF2357F20 Renesas Electronics America, DF2357F20 Datasheet - Page 202

• Manufacturer Part Number: DF2357F20
• Description: IC H8S MCU FLASH 5V 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2357F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.2.1
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be selected by means of
the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR
is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.2.2
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination
address. The upper 8 bits of the transfer address are automatically set to H'FF.
Whether IOAR functions as the source address register or as the destination address register can be selected by means of
the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
Rev.6.00 Oct.28.2004 page 172 of 1016
REJ09B0138-0600H
Bit
MAR
Initial value :
R/W
Bit
MAR
Initial value :
R/W
Bit
IOAR
Initial value :
R/W
Memory Address Registers (MAR)
I/O Address Register (IOAR)
:
:
:
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
31
15
15
—
—
0
*
*
30
14
14
—
—
0
*
*
29
13
13
—
—
0
*
*
28
12
12
—
—
0
*
*
27
11
11
—
—
0
*
*
26
10
10
—
—
0
*
*
25
—
—
0
9
*
9
*
24
—
— R/W R/W R/W R/W R/W R/W R/W R/W
0
8
*
8
*
23
*
7
*
7
*
22
*
6
*
6
*
21
*
5
*
5
*
20
*
4
*
4
*
19
*
3
*
3
*
18
*
2
*
2
*
17
*
1
*
1
*
16
0
*
0
*
*
*: Undefined
*: Undefined