EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 180

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

10 ADC (Analog to Digital Converter)
10.1
Setup and Configuration
The EM35x ADC is a first-order sigma-delta converter with the following features:
Figure 10-1 shows the basic ADC structure.
While the ADC Module supports both single-ended and differential inputs, the ADC input stage always operates
in differential mode. Single-ended conversions are performed by connecting one of the differential inputs to
VREF/2 while fully differential operation uses two external inputs.
Note: The regulator input voltage, VDD_PADS, cannot be measured using the ADC, but it can be measured
through Ember software.
To use the ADC follow this procedure, described in more detail in the next sections:
Resolution of up to 14 bits
Sample times as fast as 5.33 µs (188 kHz)
Differential and single-ended conversions from six external and four internal sources
One voltage range (differential): -VREF to +VREF
Choice of internal or external VREF
internal VREF may be output to PB0 or external VREF may be derived from PB0
Digital offset and gain correction
Dedicated DMA channel with one-shot and continuous operating modes
Configure any GPIO pins to be used by the ADC in analog mode.
Configure the voltage reference (internal or external).
Set the offset and gain values.
If using DMA, reset the ADC DMA, define the DMA buffer, and start the DMA in the proper transfer mode.
Figure 10-1. ADC Block Diagram
Final
10-1
EM351 / EM357
120-035X-000G