EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 55

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

7.2
Configuration
Each of the three GPIO ports has the following registers whose low-order eight bits correspond to the port’s
eight GPIO pins:
In addition to these registers, each port has a pair of configuration registers, GPIO_PxCFGH and GPIO_PxCFGL.
These registers specify the basic operating mode for the port’s pins. GPIO_PxCFGL configures the pins Px[3:0]
and GPIO_PxCFGH configures the pins Px[7:4]. For brevity, the notation GPIO_PxCFGH/L refers to the pair of
configuration registers.
Five GPIO pins (PA6, PA7, PB6, PB7 and PC0) can sink and source higher current than standard GPIO outputs.
Refer to Table 2-5, Digital I/O Specifications in Chapter 2, Electrical Characteristics, for more information.
Each pin has a 4-bit configuration value in the GPIO_PxCFGH/L register. The various GPIO modes and their
4-bit configuration values are shown in Table 7-1.
If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers in
addition to GPIO_PxCFGH/L determine which peripheral controls the output.
Several GPIOs share an alternate output with Timer 2 and the Serial Controllers. Bits in Timer 2’s TIM2_OR
register control routing Timer 2 outputs to different GPIOs. Bits in Timer 2’s TIM2_CCER register enable Timer
2 outputs. When Timer 2 outputs are enabled they override Serial Controller outputs. Table 7-2 indicates the
GPIO mapping for Timer 2 outputs depending on the bits in the register TIM2_OR. Refer to Chapter 9, General
Purpose Timers for complete information on timer configuration.
GPIO Mode
Analog
Input (floating)
Input (pull-up or
pull-down)
Output (push-
pull)
Output (open-
drain)
Alternate Output
(push-pull)
Alternate Output
(open-drain)
GPIO_PxIN (input data register) returns the pin level (unless in analog mode).
GPIO_PxOUT (output data register) controls the output level in normal output mode.
GPIO_PxCLR (clear output data register) clears bits in GPIO_PxOUT.
GPIO_PxSET (set output data register) sets bits in GPIO_PxOUT.
GPIO_PxWAKE (wake monitor register) specifies the pins that can wake the EM35x.
GPIO_PxCFGH/L Description
0xD
0x0
0x4
0x8
0x1
0x5
0x9
Table 7-1. GPIO Configuration Modes
Analog input or output. When in analog mode, the digital input
(GPIO_PxIN) always reads 1.
Digital input without an internal pull up or pull down. Output is
disabled.
Digital input with an internal pull up or pull down. A set bit in
GPIO_PxOUT selects pull up and a cleared bit selects pull down.
Output is disabled.
Push-pull output. GPIO_PxOUT controls the output.
Open-drain output. GPIO_PxOUT controls the output. If a pull up is
required, it must be external.
Push-pull output. An onboard peripheral controls the output.
Open-drain output. An onboard peripheral controls the output. If a
pull up is required, it must be external.
Final
7-2
EM351 / EM357
120-035X-000G